Embedded Files
【VHDL記述】
library IEEE;
use IEEE.std_logic_1164.all;
entity DECODER_7SEG is
port ( D : in std_logic_vector(3 downto 0);
Y : out std_logic_vector(6 downto 0));
end DECODER_7SEG;
architecture DATAFLOW of DECODER_7SEG is
begin
process ( D )
begin
-- case文
case D is
when "0000" => Y <= "0111111"; -- 0
when "0001" => Y <= "0000110"; -- 1
when "0010" => Y <= "1011011"; -- 2
when "0011" => Y <= "1001111"; -- 3
when "0100" => Y <= "1100110"; -- 4
when "0101" => Y <= "1101101"; -- 5
when "0110" => Y <= "1111101"; -- 6
when "0111" => Y <= "0000111"; -- 7
when "1000" => Y <= "1111111"; -- 8
when "1001" => Y <= "1101111"; -- 9
when "1010" => Y <= "1110111"; -- A
when "1011" => Y <= "1111100"; -- B
when "1100" => Y <= "0111001"; -- C
when "1101" => Y <= "1011110"; -- D
when "1110" => Y <= "1111001"; -- E
when "1111" => Y <= "1110001"; -- F
when others => Y <= "XXXXXXX";
end case;
end process;
end DATAFLOW;
【Verilog-HDL記述】
module DECODER_7SEG (
D,
Y
);
input[ 3 : 0 ] D;
output[ 6 : 0 ] Y;
assign Y = FUNC_Y( D );
// function定義
function[ 3 : 0 ] FUNC_Y;
input[ 3 : 0 ] D;
begin
// case文による出力の場合分け
case ( D )
4'b0000 : FUNC_Y = 7'b0111111; // 0
4'b0001 : FUNC_Y = 7'b0000110; // 1
4'b0010 : FUNC_Y = 7'b1011011; // 2
4'b0011 : FUNC_Y = 7'b1001111; // 3
4'b0100 : FUNC_Y = 7'b1100110; // 4
4'b0101 : FUNC_Y = 7'b1101101; // 5
4'b0110 : FUNC_Y = 7'b1111101; // 6
4'b0111 : FUNC_Y = 7'b0000111; // 7
4'b1000 : FUNC_Y = 7'b1111111; // 8
4'b1001 : FUNC_Y = 7'b1101111; // 9
4'b1010 : FUNC_Y = 7'b1110111; // A
4'b1011 : FUNC_Y = 7'b1111100; // B
4'b1100 : FUNC_Y = 7'b0111001; // C
4'b1101 : FUNC_Y = 7'b1011110; // D
4'b1110 : FUNC_Y = 7'b1111001; // E
4'b1111 : FUNC_Y = 7'b1110001; // F
default : FUNC_Y = 7'bxxxxxxx;
endcase
end
endfunction
endmodule
【合成結果】
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