【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity COMPARATOR is

port ( A, B : in std_logic_vector(3 downto 0);

Y : out std_logic );

end COMPARATOR;

architecture DATAFLOW of COMPARATOR is

begin

process ( A, B )

begin

if ( A > B ) then

Y <= '1';

else

Y <= '0';

end if;

end process;

end DATAFLOW;

【Verilog-HDL記述】

module COMPARATOR (

A, B,

Y

);

input[ 3 : 0 ] A, B;

output Y;

assign Y = FUNC_Y( A, B );

// function定義

function FUNC_Y;

input[ 3 : 0 ] A, B;

begin

if ( A > B ) begin

FUNC_Y = 1'b1;

end else begin

FUNC_Y = 1'b0;

end

end

endfunction

endmodule