【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity RS_FF is

port ( R, S : in std_logic;

Q, Qnot : out std_logic );

end RS_FF;

architecture STRUCTURE of RS_FF is

signal S1, S2 : std_logic;

begin

S1 <= R nor S2;

S2 <= S nor S1;

Q <= S1;

Qnot <= S2;

end STRUCTURE;

【Verilog-HDL記述】

module RS_FF (

R, S,

Q, Qnot

);

input R, S;

output Q, Qnot;

assign Q = ~( R | Qnot );

assign Qnot = ~( S | Q );

endmodule