【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity ROM is -- 記憶容量 2**AL(words)

generic( WL : integer := 8; -- ワード長(bits)

AL : integer := 4 ); -- アドレスバス長(bits)

port( RE : in std_logic;

ADDR : in std_logic_vector(AL-1 downto 0);

DATA_OUT : out std_logic_vector(WL-1 downto 0));

end ROM;

architecture BEHAVIOR of ROM is

subtype WORD is std_logic_vector(WL-1 downto 0);

type MEMORY is array ( 0 to 2**AL-1 ) of WORD;

constant MEM : MEMORY := (

"01101100", "10000000", "01100010", "00000000",

"10110001", "10101010", "00000001", "00110011",

"00000100", "01110100", "10000001", "00001111",

"00000000", "00000000", "00000000", "00000000" );

begin

READ_OP: process( RE, ADDR ) begin

if ( RE = '1' ) then

DATA_OUT <= MEM(conv_integer(ADDR));

end if;

end process;

end BEHAVIOR;

【Verilog-HDL記述】

module ROM (

RE, ADDR,

DATA_OUT

);

// 記憶容量 2**AL(words)

parameter WL = 8; // ワード長(bits)

parameter AL = 4; // アドレスバス長(bits)

input RE;

input[ AL-1 : 0 ] ADDR;

output[ WL-1 : 0 ] DATA_OUT;

reg[ WL-1 : 0 ] DATA_OUT;

always @ ( RE or ADDR ) begin : READ_OP

if ( RE ) begin

DATA_OUT <= FUNC_MEM( ADDR );

end

end

function[ WL-1 : 0 ] FUNC_MEM;

input[ AL-1 : 0 ] ADDR;

begin

case ( ADDR )

0: FUNC_MEM = 'b01101100;

1: FUNC_MEM = 'b10000000;

2: FUNC_MEM = 'b01100010;

3: FUNC_MEM = 'b00000000;

4: FUNC_MEM = 'b10110001;

5: FUNC_MEM = 'b10101010;

6: FUNC_MEM = 'b00000001;

7: FUNC_MEM = 'b00110011;

8: FUNC_MEM = 'b00000100;

9: FUNC_MEM = 'b01110100;

10: FUNC_MEM = 'b10000001;

11: FUNC_MEM = 'b00001111;

12: FUNC_MEM = 'b00000000;

13: FUNC_MEM = 'b00000000;

14: FUNC_MEM = 'b00000000;

15: FUNC_MEM = 'b00000000;

endcase

end

endfunction

endmodule