【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity RAM is -- 記憶容量 2**AL(words)

generic( WL : integer := 8; -- ワード長(bits)

AL : integer := 8 ); -- アドレスバス長(bits)

port( RW : in std_logic;

ADDR : in std_logic_vector(AL-1 downto 0);

DATA_IN : in std_logic_vector(WL-1 downto 0);

DATA_OUT : out std_logic_vector(WL-1 downto 0));

end RAM;

architecture BEHAVIOR of RAM is

subtype WORD is std_logic_vector(WL-1 downto 0);

type MEMORY is array ( 0 to 2**AL-1 ) of WORD;

signal MEM : MEMORY;

begin

READ_OP: process( RW, ADDR ) begin

if ( RW = '1' ) then

DATA_OUT <= MEM(conv_integer(ADDR));

end if;

end process;

WRITE_OP: process( RW, ADDR ) begin

if ( RW = '0' ) then

MEM(conv_integer(ADDR)) <= DATA_IN;

end if;

end process;

end BEHAVIOR;

【Verilog-HDL記述】

module RAM (

RW, ADDR,

DATA_IN,

DATA_OUT

);

// 記憶容量 2**AL(words)

parameter WL = 8; // ワード長(bits)

parameter AL = 4; // アドレスバス長(bits)

input RW;

input[ AL-1 : 0 ] ADDR;

input[ WL-1 : 0 ] DATA_IN;

output[ WL-1 : 0 ] DATA_OUT;

reg[ WL-1 : 0 ] DATA_OUT;

reg[ WL-1 : 0 ] MEM[ 0 : (1<<AL)-1 ];

always @ ( RW or ADDR ) begin : READ_OP

if ( RW ) begin

DATA_OUT <= MEM[ ADDR ];

end

end

always @ ( RW or ADDR ) begin : WRITE_OP

if ( !RW ) begin

MEM[ ADDR ] <= DATA_IN;

end

end

endmodule