【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity UP_DOWN_COUNTER is

generic( N : integer := 4 ); -- FFの数(2**N進カウンタ)

port(

CLK, RESET, UD : in std_logic;

COUT : out std_logic_vector(N-1 downto 0));

end UP_DOWN_COUNTER;

architecture RTL of UP_DOWN_COUNTER is

signal COUNT_TMP : std_logic_vector(N-1 downto 0);

begin

process( CLK, RESET ) begin

if (RESET = '1') then

COUNT_TMP <= (others => '0');

elsif (CLK'event and CLK = '1') then

if (UD = '1') then

COUNT_TMP <= COUNT_TMP + 1;

else

COUNT_TMP <= COUNT_TMP - 1;

end if;

end if;

end process;

COUT <= COUNT_TMP;

end RTL;

【Verilog-HDL記述】

module UP_DOWN_COUNTER (

CLK, RESET, UD,

COUT

);

parameter N = 4; // FFの数(2**N進カウンタ)

input CLK, RESET, UD;

output[ N-1 : 0 ] COUT;

reg[ N-1 : 0 ] COUNT_TMP;

always @ ( posedge CLK or posedge RESET ) begin

if ( RESET ) begin

COUNT_TMP <= 0;

end else begin

if ( UD ) begin

COUNT_TMP <= COUNT_TMP + 1;

end else begin

COUNT_TMP <= COUNT_TMP - 1;

end

end

end

assign COUT = COUNT_TMP;

endmodule