【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity JOHNSON_COUNTER is

generic( N : integer := 4 ); -- FFの数(Nビットジョンソンカウンタ)

port( CK, RESET : in std_logic;

Y : out std_logic_vector(N-1 downto 0));

end JOHNSON_COUNTER;

architecture BEHAVIOR of JOHNSON_COUNTER is

signal COUNT : std_logic_vector(N-1 downto 0);

begin

process( RESET, CK ) begin

if ( RESET = '1' ) then

COUNT <= (others => '0');

elsif ( CK'event and CK = '1' ) then

COUNT <= COUNT(N-2 downto 0) & (not COUNT(N-1));

end if;

end process;

Y <= COUNT;

end BEHAVIOR;

【Verilog-HDL記述】

module JOHNSON_COUNTER (

CK, RESET,

Y

);

parameter N = 4; // FFの数(Nビットジョンソンカウンタ)

input CK, RESET;

output[ N-1 : 0 ] Y;

reg[ N-1 : 0 ] COUNT;

always @ ( posedge CK or posedge RESET ) begin

if ( RESET ) begin

COUNT <= 0;

end else begin

COUNT <= { COUNT[ N-2 : 0 ], ~COUNT[ N-1 ] };

end

end

assign Y = COUNT;

endmodule