【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity GRAY_CODE_COUNTER is

generic( N : integer := 4 ); -- FFの数(Nビットグレイコードカウンタ)

port( CK, RESET : in std_logic;

Y : out std_logic_vector(N-1 downto 0));

end GRAY_CODE_COUNTER;

architecture BEHAVIOR of GRAY_CODE_COUNTER is

signal COUNT : std_logic_vector(N-1 downto 0);

begin

process( RESET, CK ) begin

if ( RESET = '1' ) then

COUNT <= (others => '0');

elsif ( CK'event and CK = '1' ) then

COUNT <= COUNT + 1;

end if;

end process;

process (COUNT) begin

Y(N-1) <= COUNT(N-1);

for I in N-2 downto 0 loop

Y(I) <= COUNT(I+1) xor COUNT(I);

end loop;

end process;

end BEHAVIOR;

【Verilog-HDL記述】

module GRAY_CODE_COUNTER (

CK, RESET,

Y

);

parameter N = 4; // FFの数(Nビットグレイコードカウンタ)

input CK, RESET;

output[ N-1 : 0 ] Y;

reg[ N-1 : 0 ] COUNT;

always @ ( posedge CK or posedge RESET ) begin

if ( RESET ) begin

COUNT <= 0;

end else begin

COUNT <= COUNT + 1;

end

end

assign Y = FUNC_Y( COUNT );

function[ N-1 : 0 ] FUNC_Y;

input[ N-1 : 0 ] COUNT;

integer I;

begin

FUNC_Y[ N-1 ] = COUNT[ N-1 ];

for ( I = N-2; I >= 0; I = I-1 ) begin

FUNC_Y[ I ] = COUNT[ I+1 ] ^ COUNT[ I ];

end

end

endfunction

endmodule