【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity MODULO is

generic( W : integer := 4 );

port ( X, Y : in std_logic_vector(W-1 downto 0);

Z : out std_logic_vector(W-1 downto 0));

end MODULO;

architecture STUDENT_3 of MODULO is

constant ZV : std_logic_vector(Y'high-1 downto 0) := (others => '0');

begin

process ( X, Y )

variable TMP : std_logic_vector(X'length+Y'length-2 downto 0);

begin

TMP := ZV & X;

for I in X'range loop

if ( TMP(Y'high+I downto I) >= Y ) then

TMP(Y'high+I downto I) := TMP(Y'high+I downto I) - Y;

end if;

end loop;

Z <= TMP(Y'range);

end process;

end STUDENT_3;

【Verilog-HDL記述】

※ この回路のVerilog-HDL記述は、割愛させて頂きます。ご了承下さい。