【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity JK_FF is

port( CK, J, K : in std_logic;

Q, Qnot : out std_logic );

end JK_FF;

architecture BEHAVIOR of JK_FF is

signal INPUT : std_logic_vector(2 downto 0);

signal TMP : std_logic;

begin

INPUT <= CK & J & K;

process ( INPUT ) begin

case INPUT is

when "101" => TMP <= '0';

when "110" => TMP <= '1';

when "111" => TMP <= not TMP;

when others => null;

end case;

end process;

Q <= TMP;

Qnot <= not TMP;

end BEHAVIOR;

【Verilog-HDL記述】

module JK_FF (

CK, J, K,

Q, Qnot

);

input CK, J, K;

output Q, Qnot;

wire[ 2 : 0 ] INPUT;

reg TMP;

assign INPUT = { CK, J, K };

always @ ( INPUT ) begin

case ( INPUT )

3'b101: TMP <= 1'b0;

3'b110: TMP <= 1'b1;

3'b111: TMP <= ~TMP;

endcase

end

assign Q = TMP;

assign Qnot = ~TMP;

endmodule