【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity D_FF is

port( CK, D : in std_logic;

Q : out std_logic );

end D_FF;

architecture BEHAVIOR of D_FF is

begin

process ( CK, D ) begin

if ( CK = '1' ) then

Q <= D;

end if;

end process;

end BEHAVIOR;

【Verilog-HDL記述】

module D_FF (

CK, D,

Q

);

input CK, D;

output Q;

reg Q;

always @ ( CK or D ) begin

if ( CK == 1'b1 ) begin

Q <= D;

end

end

endmodule