張孟洲(Meng-Chou Chang)

張孟洲 (Meng-Chou Chang) 論文著作

(A) 期刊論文(Journal Papers)

[1] Meng-Chou Chang, Po-Hung Yang, and Ze-Gang Pan, “Register-Less NULL Convention Logic,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 3, pp. 314-318, Mar. 2017. [SCI]

[2] Meng-Chou Chang, Kai-Lun He, and Yu-Chieh Wang, “Design of Ternary Content-Addressable Memories with Dynamically Power-gated Storage Cells Using FinFETs,” Electronics (ISSN: 1450-5843), vol. 20, no. 1, pp. 9-15, June 2016. [EI]

[3] Meng-Chou Chang, Ming-Hsun Hsieh, and Po-Hung Yang, “Low-Power Asynchronous NCL Pipelines With Fine-Grain Power Gating and Early Sleep,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 12, pp. 957-961, Dec. 2014. [SCI]

[4] Meng-Chou Chang and Wei-Hsiang Chang, “Asynchronous Fine-Grain Power-Gated Logic,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 6, pp. 1143-1153, Jun. 2013. [SCI Expanded]

[5] Shu-Ming Tseng, Yao-Teng Hsu, Meng-Chou Chang, and Hsiao-Lung Chan, “A Notebook PC Based Real-Time Software Radio DAB Receiver,” IEICE Transactions on Communications, Dec. 2006, Vol. E89-B, No.12. pp. 3208-3214. [SCI]

[6] Shu-Ming Tseng, Meng-Chou Chang, Hsiao-Lung Chan, and Yao-Teng Hsu, “A Simplified Decoding Scheme of an Optical Transform Domain Error Control Code,” Journal of Optical Communications, Vol. 27, 2006, pp. 238-240. [EI]

[7] Meng-chou Chang, and Yu-wen Chou, 2002, March, Vol. 149, No. 2, “Branch Prediction using Both Global and Local History Information,” IEE Proceedings-Computers and Digital Techniques, pp.33-38. [屬於SCI/EI]

[8] Meng-chou Chang, Ong-xing Lin, and Yu-wen Chou, 2001, December, Vol. 4, No. 4, “A New Filtering Scheme for Improving Branch Prediction Accuracy,” Communications of IICM, pp. 17-23.

[9] Meng-chou Chang and Feipei Lai, 1996, March, Vol.45, No.3, “Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme,” IEEE Transactions on Computers, pp. 278-293. [屬於SCI/EI] 本論文獲得國科會八十五學年度甲種研究獎勵費（工程科學類）

[10] Meng-chou Chang, Feipei Lai, and Wei-chao Chen, 1996, October, Vol.15, No.4, “Image Shading Taking into Account Relativistic Effects,” ACM Transactions on Graphics, pp. 265-300. [屬於SCI/EI] 本論文獲得國科會八十六學年度甲種研究獎勵費（工程科學類）

[11] Meng-chou Chang and Feipei Lai, 1994, vol.17, no.2, “A Superscalar Micro-architecture Supporting Aggressive Instruction Scheduling,” Journal of the Chinese Institute of Engineers, pp.151-167. [屬於EI]

[12] Meng-chou Chang and Feipei Lai, 1993, vol.17, no.3, ``Exploiting Instruction-Level Parallelism with the Conjugate Register File Scheme,'' Proc. Natl. Sci. Counc., pp.139-153. [屬於EI]

(B) 研討會論文(Conference Papers)

[1] Chun-Ying Chen and Meng-Chou Chang, “ Using Deep Neural Networks to Classify the Severity of Diabetic Retinopathy,” in Proceedings of 2022 IEEE International Conference on Consumer Electronics - Taiwan, Taipei, Taiwan, Jul. 06-08, 2022, pp. 241-242.

[2] Ko-Hua Lai and Meng-Chou Chang, “Classification of Tissue Types in Histological Colorectal Cancer Images Using Residual Networks,” in Proceedings of 2019 IEEE 8th Global Conference on Consumer Electronics, Osaka, Japan, Oct. 15-18, 2019, pp. 299-300.

[3] 黃鈺鈞、張孟洲, “以深度學習進行心電圖之異常心律偵測,” in Proceedings of 2019 17th Conference on Microelectronics Technology and Applications (2019 C’META), May 24, 2019, pp. 214-219.

[4] 陳要綸、張孟洲, “使用奈米碳管電晶體元件的低功率分段式內容可定址記憶體設計,” in Proceedings of 2019 17th Conference on Microelectronics Technology and Applications (2019 C’META), May 24, 2019, pp. 170-173.

[5] Meng-Chou Chang, Ze-Gang Pan, and Jyun-Liang Chen, “Hardware Accelerator for Boosting Convolution Computation in Image Classification Applications,” in Proceedings of 2017 IEEE 6th Global Conference on Consumer Electronics, Nagoya, Japan, Oct. 24-27, 2017, pp. (POS-1) 1-2.

[6] Meng-Chou Chang and Siao-Siang Liu, “FinFET-Based TCAMs with Matchline-Accelerating Sense Amplifiers,” in Proceedings of 2016 IEEE 5th Global Conference on Consumer Electronics, Kyoto, Japan, Oct. 11-14, 2016, pp. (POS-3) 1-2.

[7] Meng-Chou Chang and Siao-Siang Liu, “Design of a FinFET-based TCAM with Matchline-Accelerating Sense Amplifiers,” in Proceedings of the 27th VLSI Design/CAD Symposium, Aug. 2-5, 2016, pp. (S6-4) 1-2.

[8] Meng-Chou Chang and Kai-Lun He, “Design of Low-Power FinFET-Based TCAMs with Unevenly-Segmented Matchlines for Routing Table Applications,” in Proceedings of the 11th IEEE International Conference on ASIC (ASICON 2015), November 3-6, 2015, pp. (P2-42) 1-4.

[9] Meng-Chou Chang and Kai-Lun He, “FinFET-Based TCAMs with Unevenly-Segmented Matchlines for Routing Table Applications,” in Proceedings of the 26th VLSI Design/CAD Symposium, Aug. 4-7, 2015, pp. (p02-4) 1-2.

[10] Meng-Chou Chang, Kai-Lun He, and Yu-Chieh Wang, “Design of Asymmetric TCAM (Ternary Content-Addressable Memory) Cells Using FinFET,” in Proceedings of 2014 IEEE 3rd Global Conference on Consumer Electronics, Makuhari Messe, Tokyo, Japan, Oct. 7-10, 2014, pp. 358-359.

[11] Meng-Chou Chang, Kai-Lun He, and Yu-Chieh Wang, “Design of Ternary Content-Addressable Memories Using FinFET,” in Proceedings of the 24th VLSI Design/CAD Symposium, Aug. 6-9, 2013, p1-3, pp. 1-2.

[12] Meng-Chou Chang and Shih-Ju Tsai, “A Low-Power Ternary Content-Addressable Memory Using Pulse Current Based Match-Line Sense Amplifiers,” in Proceedings of the 10th IEEE International Conference on ASIC (ASICON 2013), Oct. 28-31, 2013, pp. (P1-12) 1-4.

[13] Meng-Chou Chang, Ming-Hsun Hsieh and Shih-Ju Tsai, "Design of a Low-Power Content-Addressable Memory Using Double-Feedback Match-Line Sense Amplifiers," 2012 International Conference on Electrical Engineering and Computer Science (ICMEE/EECS2012), June 23-24, 2012, (Lecture Notes in Electrical Engineering 178, Advances in Mechanical and Electronic Engineering, Vol.3, pp. 433-438). [EI]

[14] Meng-Chou Chang and Yen-Ting Kuo, "Design of a Two-Phase Adiabatic Content-Addressable Memory," 2011 International Conference on Electric and Electronics (EEIC2011), June 20-22, 2011, (Lecture Notes in Electrical Engineering 100, Communication Systems and Information Technology, Vol.4, pp. 577-583). [EI]

[15] Meng-Chou Chang and Yen-Ting Kuo, "Design of a Two-Phase Adiabatic Content-Addressable Memory," the 22nd VLSI Design / CAD Symposium, August 2-5, 2011, pp.328-331.

[16] Meng-Chou Chang and Da-Sen Shiau," Comparison of Two Data Hazard Handling Schemes for Asynchronous Pipelined Processors," 2010 3rd IEEE International Conference on Computer Science and Information Technology (ICCSIT), July 9-11, 2010, vol.4, pp. 36-40.

[17] Meng-Chou Chang and Chia-Chang Tsai, “Handshaking Quasi-Adiabatic Logic,” The 52nd. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2009), Cancún, México, August 2-5, 2009, pp.531-534.

[18] Meng-Chou Chang and Da-Sen Shiau, “Design of an Asynchronous Pipelined Processor,” 2008 International Conference on Communications, Circuits and System (ICCCAS 2008), May 25-27, 2008, pp. 1226-1229.

[19] Meng-Chou Chang and Da-Sen Shiau, “Design of an Asynchronous Pipelined Processor by Using the Balsa Language,” The 19th VLSI Design/CAD Symposium, August 5-8, 2008, pp. 38-41.

[20] Meng-Chou Chang and Yong-Jie Cheng, “Motion Detection by Using Entropy Image and Adaptive State-Labeling Technique,’’ in Proceedings of the 2007 IEEE International Symposium on Circuits and Systems, May 27-30, 2007, New Orleans, pp. 3667-3670. [屬於EI]

[21] Da-Sen Shiau and Meng-Chou Chang, “Impact of Different Balsa Coding Styles on the Performance and Cost of Asynchronous Pipelined Circuits,” The 5^th Conference on Microelectronics Technology & Applications, May 18, 2007, pp. 133-134.

[22] Meng-chou Chang and Jung-shan Chien, “An Adaptive Search Algorithm Based on Block Classification for Fast Block Motion Estimation,” in Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, May 21-24, 2006. Island of Kos, Greece, pp. 3982-3985. [屬於EI]

[23] Shu-Ming Tseng, Yao-Teng Hsu, Meng-Chou Chang, and Hsiao-Lung Chan, “A Notebook PC Based Real-Time Software Radio DAB Receiver,” in Proceedings of the SICE - ICASE International Joint Conference 2006 (SICE - ICASE 2006), Busan, Korea, October 18-21, 2006.

[24] Meng-chou Chang, Che-wei Chang, Chang-hong Hsia and Hsiao-lung Chan, 2005, November, “Design of an Electrocardiogram QRS Complex Detector Employing Tompkins Method and Template Matching,” in Proceedings of 2005 Workshop on Consumer Electronics and Signal Processing, November 17-18, 2005.

[25] Meng-chou Chang, Rong-yau Tsai, and Che-wei Chang, 2004, August, “Design of an Embedded Superscalar Processor Compatible with the ARMv4 Instruction Set,” 2004 VLSI Design/CAD Symposium, p.12.

[26] Meng-chou Chang, Zong-xin Lin, Che-wei Chang, Hsiao-lung Chan, and Wu-shiung Feng, 2004, December, “Design of a System-on-Chip for ECG Signal Processing,” 2004 IEEE Asia-Pacific Conference on Circuit and Systems, December 6-9, pp. 441-444. [屬於EI]

[27] Meng-chou Chang, Zong-xin Lin, Rong-yau Tsai, Hsiao-lung Chan, and Wu-shiung Feng, 2003, December, “Design of an ARM-based System-on-Chip for Real-time QRS Detection in Electrocardiograms,” 2003 International Conference on Informatics, Cybernetics, and Systems, pp.319-324.

[28] Meng-chou Chang, Ting-yu Chiu, and Chih-pei Chang, 2003, December, “Employing both inter-branch and intra-branch correlation to improve the accuracy of branch prediction for superscalar processor,” National Computer Symposium 2003, pp. 2280-2284.

[29] Shu-Ming Tseng; Yibin Zheng; Yao-Teng Hsu; and Meng-Chou Chang, 2002, “Fuzzy adaptive parallel interference cancellation and vector channel prediction for CDMA in fading channels,” IEEE International Conference on Communications (ICC 2002),Vol. 1, pp 252 –256. [屬於EI]

[30] Meng-chou Chang and Yu-wen Chou, 2001, July, “Improving the Accuracy of Branch Prediction for Superscalar Processors by Employing Both the Global and Local Branch History Information,” in Proceedings of The Second International Conference on Parallel and Distributed Computing, Applications, and Techniques, pp.252-258.

[31] Yeong-Chang Maa, Meng-chou Chang, Horng-Jye Chen, Shiaw-Shian Yu, Bao-Shuh Paul Lin, 1996, April, “Designing a Shared Memory SMP Cluster,” in Proceedings of 1996 International conference on Computer System Technology for Industrial Applications, pp. 72-80.

[32] Meng-chou Chang, Feipei Lai, and Rung-ji Shang, 1992, Dec., ``Exploiting Instruction-Level Parallelism with the Conjugate Register File Scheme,'' in Proceedings of the 25th International Symposium on Microarchitecture (sponsored by IEEE and ACM), pp.29-32. [屬於EI]

[33] Feipei Lai and Meng-chou Chang, 1992, May,``Enhancing Boosting with Semantic Register in a Superscalar Processor,'' in Proceedings of the 19th Annual International Symposium on Computer Architecture (ACM SIGARCH Computer Architecture News, vol.20, no.4), p.430. [屬於EI]

[34] Yuh-Haur Lin, Feipei Lai, and Meng-chou Chang, 1991, May, ``ARES - Architecture REinforcing Superscalar,'' in Proceedings of 1991 International Symposium on VLSI Technology, Systems, and Applications, pp.338-343.

近年研究