Takagi-Toprasertpong Laboratory
Department of Electrical Engineering and Information Systems, The University of Tokyo
Takagi-Toprasertpong Laboratory
Department of Electrical Engineering and Information Systems, School of Engineering, The University of Tokyo
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Takagi-Toprasertpong Laboratory is jointly operating with Takenaka Laboratory.
What's new!
2024/02/16 Zuocheng Cai received 22nd IEEE EDS Japan Joint Chapter Student Award.
2023/09/5 Chia-Tsong Chen recieved SSDM Best Student Award (BSA).
2023/06/01 Dr. Kasidit Toprasertpong has been promoted to Associate Professor.
2023/03/23 Kei Sumita received 2022 Dean's Award for Best Doctoral thesis and Distinguished Doctoral Thesis Award.
2023/03/16 Kei Sumita, Chia-Tsong Chen, Dr. Kasidit Toprasertpong, Prof. Mitsuru Takenaka, Prof. Shinichi Takagi received 14th JSAP Silicon Technology Division Paper Award.
2023/02/16 Eishin Nako received 21st IEEE EDS Japan Joint Chapter Student Award.
2022/09/20 Eishin Nako received 52nd JSAP Young Scientist Presentation Award.
2022/06/13 Press release about our research on FeFET reservoir computing for speech recognition. The summary of this work is also published in NIKKEI (Japanese) and TechXplore (English).
See here for older posts.
The performance of Si LSIs has been enhanced over 40 years by increasing the number of transistors, according to the Moore's law. However, the device scaling is approaching to the physical limitation because the gate length has been already scaled to less than 20 nm. In the next 10 - 20 years, the device scaling might end, leading to no further enhancement in the LSI performance by the device scaling.
On the other hand, much more computing power will be strongly required because of the emergence of new IoT and AI applications. Hence, the next-generation computing technologies have intensively been investigated to enhance the LSI performance without the device scaling. We are conducting such researches on next-generation semiconductor devices for AI and IoT applications. We are mainly focusing on the the technology development based on Si CMOS, and the heterogeneous integration of III-V semiconductors, Ge, and ferroelectric materials on the Si platform.
Main research
HfO2-based Ferroelectric devices
Reservoir computing based on ferroelectric devices
Ultra-thin III-V MOSFET for CMOS 3D-integration
Ultra-thin Ge MOSFET for CMOS 3D-integration
Understanding of Si CMOS operation under ultra-low temperature for quantum computing application
