Welcome to DarkLife
Developed in a magic night of 19 Aug, 2018 between 2am and 8am, the DarkRISCV softcore started as an proof of concept for the opensource RISC-V instruction set.
The general concept was based in my other early 16-bit RISC processors and composed by a simplified two stage pipeline working with a two phase clock, where a instruction is fetch from a instruction memory in the first clock and then the instruction is decoded/executed in the second clock. The pipeline is overlapped without interlocks, in a way that the DarkRISCV can reach the performance of one clock per instruction most of time, except by a taken branch, where one clock is lost in the pipeline flush. Of course, in order to perform read operations in blockrams in a single clock, a two-phase clock is required, in a way that no wait states are required. As result, the code is very compact, with around three hundred lines of obfuscated but beautiful Verilog code. After lots of exciting sleepless nights of work and the help of lots of colleagues, the DarkRISCV reached a very good quality result, in a way that the code compiled by the standard GCC for RV32I worked fine. [github.com/darklife/darkriscv]
Some old, but interesting, free research papers:
- TE811: Signal Codification Simulation and Techniques (UFPR)
- TE815: GNS3 Network Simulator Tutorial (UFPR)
- TE823: Delta-Sigma Converter ASIC (UFPR)
The papers are available in the [Google Drive]
Darklife supported some projects across the 90's in the area of Graphic Interfaces, Operating System Design and Microcontroller Development Support. Althrough some projects are obsolete or even incomplete, they may be used nowadays as reference for new projects.