PLEASE NOTE: All content on the page subject to change until September 30, 2025.
3 credit hours, takes approximately 12-15 hours/week including lecture.
Lectures: TUE/THUR, 2:00-3:15PM, ECCR 1B55. Videos of the lectures will be posted and available on demand to enrolled students.
Projects: Will require checkout of development kits*
Prerequisites: Knowledge of assembly and C Programming, Digital Logic Design, and basic computer architecture. Students should have a first course in each of these subjects. The corresponding CU-Boulder courses are ECEN 2120/2350, ECEN 3100/3350, and ECEN 1030/1310/CSCI 1300. In particular, ability to perform tasks like write a string copy function in C and design sequential circuits using Karnaugh maps is needed.
Course Materials
Textbooks (CU bookstore, and also online through the CU Library)
Embedded SoPC Design with NIOS II Processor and Verilog Examples, by Pong P. Chu; ISBN 978-1-118-01103-4.
[optional] Rapid Prototyping of Digital Systems, SOPC Edition, by Hamblen, Hall, and Furman
PC Requirements: 1 GHz+ processor, 8 GB of RAM, 50 GB of free hard drive space running either Windows 10 or 11 or a recent Linux OS which must be RHEL 6.5 or CentOS Linux 6.5 or later. Mac's have not had success running the tools in this course and are not recommended.
Required development kits*:
Altera DE10-lite. Description and purchasing here: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=english&No=1021
Microchip PolarFire SoC Discovery Kit. Description: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit
Altera DE1-SoC. Description https://www.altera.com/support/training/university/boards.tablet.html#de1-soc
*Kits will be provided to campus students in Boulder and shipped to U.S.-based distance students only (i.e. Professional Certificate students and distance degree students).
Required for Distance students: A PC with a microphone and web camera; reliable internet connection (minimum 5 megabits per second download speed).
Course will be administered on Canvas
Office hours: TuTh 4-5 pm
TA Contact Information:
Hyounjun Chang hyounjun.chang@colorado.edu
TBD
This course examines usage of Programmable Logic Devices to create system solutions. Specific design challenges inherent to this technology will be addressed using industry standard techniques and practices. We willl use recent FPGA development platforms, including platforms from Altera, Lattice and Microsemi, to design, program and construct working systems. This course assumes knowledge of Verilog or VHDL and C Programming, Digital Logic Design, and basic computer architecture.
Verilog, VHDL, OpenCL, System Verilog RTL design for FPGA and CPLD architectures
FPGA development tools flow: specify, synthesize, simulate, program and debug
Configurable embedded processors
Embedded software architecture and development
Timing closure techniques and tools
IO Standard internals (CML, LVDS, PECL, LVCMOS, SSTL, HSTL) and pin assignments
Power Distribution Network design
Use of soft-core and hard-core processors and OS options
System engineering, software-hardware integration, testing and troubleshooting
DSP algorithm impmentation in FPGAs
IP development and incorporating 3rd-party IP
High speed digital board design and layout principles
Memory Interface (DDR 1/2/3 SDRAM, HSTL SRAM, CFI)
Verification and Simulation
For more detailed information, see the syllabus at https://drive.google.com/drive/folders/1tni3qHhb3W-OAWKkhJLpQTm00Sf5qmfr?usp=sharing
Course materials include textbooks, papers, lecture slides, project guides, and other online materials.
Textbooks (CU bookstore, and also online through the CU Library)
Embedded SoPC Design with NIOS II Processor and Verilog Examples, by Pong P. Chu; ISBN 978-1-118-01103-4.
[optional] Rapid Prototyping of Digital Systems, SOPC Edition, by Hamblen, Hall, and Furman
Course website
Course lecture slides posted weekly on Canvas at TBD
Course labs and project material posted weekly on Canvas
Other online materials
The course grade will be based on in-class participation, homework assignments, quizzes, course projects, and 2 exams. The grade proportions are as follows:
Homework and class participation 20%
Course projects 30%
Quizzes 10%
Final and Mid-term Exam 40%
A complete description of the honor code can be found here .
To summarize: "Violations of the Honor Code are acts of academic dishonesty and include but are not limited to plagiarism, cheating, fabrication, aid of academic dishonesty, lying to course instructors, lying to representatives of the Honor Code, bribery or threats pertaining to academic matters, or an attempt to do any of the aforementioned violations."