E-Mail : yslee010815@chungbuk.ac.kr
Education
B.S. School of Electronic Engineering, Chungbuk National University, Republic of Korea. Mar. 2021 - Present
Research Interest
Logic Device (GAA/Nanosheet FET), Memory (DRAM cell FET), Power Device (SiC/GaN)
Device Design, Modeling & Simulation
Conferences
Y.-S. Lee, E.-C. Yun, H.-J. Park, and J.-Y. Park*, "Nanosheet FETs with an Inner Spacer Barrier for Suppression of Substrate Parasitic Effects and Punch-Through", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
Y.-S. Lee, H.-J. Park, E.-C. Yun, and J.-Y. Park*, "Investigation of a Double-Fin Gate Structure for Enhancing the Refresh Time of DRAM Cell Transistors", The Institute of Semiconductor Engineers (ISE) Summer Conference, Jul. 2026. [ PDF ], "Award" [ PDF ]
S.-Y. Jeong, S.-O. Kwon, H.-J. Park, E.-C. Yun, Y.-S. Lee, and J.-Y. Park*, "Demonstration of a Pin-Fin Type Copper Heat Sink for Reducing High Bandwidth Memory (HBM) Temperature", The Institute of Semiconductor Engineers (ISE) Summer Conference, Jul. 2026. [ PDF ]
S.-O. Kwon, S.-Y. Jeong, H.-J. Park, E.-C. Yun, Y.-S. Lee, and J.-Y. Park*, "Highly Thermally Conductive NCF Layer for Reducing Temperature Variation in High Bandwidth Memory (HBM)", The Institute of Semiconductor Engineers (ISE) Summer Conference, Jul. 2026. [ PDF ]