Sang-Min Kang
Building E10, Room #204, Chungbuk National University
E-Mail : rkdtkdlas01@chungbuk.ac.kr
Education
M.S. School of Semiconductor Engineering, Chungbuk National University, Cheongju, Republic of Korea (Mar. 2025 – Present)
B.S. School of Semiconductor Engineering, Chungbuk National University, Cheongju, Republic of Korea (Mar. 2021 – Aug. 2025)
Research Interests
Device Fabrication
– Fabrication of silicon MOSFETs with SiO₂ or HfO₂ gate dielectrics
– Electrical characterization and analysis of device performance
Reliability of Semiconductor Devices
– Development of Si/SiO₂ interface trap reduction processes for improved device performance and reliability
(Low-Temperature Deuterium Annealing, Rapid Deuterium Annealing)
– Device reliability and lifetime evaluation through electrical stress tests (HCI, PBS)
Physically Unclonable Function (PUF) Development
– Implementation of PUFs exploiting intrinsic device-level process variability
– Enhancement of PUF randomness and stability through process and device optimization
– Secure key generation using electrical parameters extracted from MOSFET devices
Technical Skills
Device Fabrication Processing (Rapid Hydrogen Annealing, Rapid Deuterium Annealing, Reactive Ion Etcher, Thermal Evaporator, Mask Aligner, Spin Coater)
Device Characterization (Alpha Step, Probe Station (Keithley 4200A, B1500A))
Publications
International Journal Papers (SCIE)
[6] S.-M. Kang, H.-J. Park, E.-C. Yun, D.-E. Bang, M.-S. Kim*, and J.-Y. Park*, "Dual-Parameter Variable Physically Unclonable Function (PUF) for Multi-level Cell Silicon MOSFETs", ACS Appl. Electron. Mater., vol. xx, no. x, pp. xxxx–xxxx, in press. [ Website ]
[5] M.-K. Lee, D.-E. Bang, S.-J. Chang, H.-J. Park, E.-C. Yun, S.-M. Kang, M.-W. Kim, D. Sohn, and J.-Y. Park*, "Rapid Hydrogen Annealing for Enhanced Device Performance and Reduced Thermal Budget", Semicond. Sci. Technol., vol. 41, no. 2, p. 025012, Feb. 2026. [ Website ]
[4] D. Sohn, M.-K. Lee, D.-E. Bang, H.-J. Park, E.-C. Yun, S.-M. Kang, M.-W. Kim, H. Jeon*, and J.-Y. Park*, "Wrap-Around Word-Line DRAM Cell Transistor Enabling Enhanced Read/Write Speed", IEEE Trans. Electron Devices, 73, no. 1, pp. 271–278, Jan. 2026. [ Website ]
[3] H.-J. Park, M.-K. Lee, E.-C. Yun, D. Sohn, M.-W. Kim, S.-M. Kang, H. Jeon, and J.-Y. Park*, "Investigation of Inner Spacer-Less Nanosheet FETs from an Off-State Current Perspective", IEEE Access, vol. 13, pp. 199876-199882, Nov. 2025. [ Website ]
[2] M.-W. Kim, H.-J. Park, M.-K. Lee, E.-C. Yun, S.-M. Kang, D.-E. Bang, T.-H. Kil, D. Sohn, and J.-Y. Park*, "Study on the Impact of Deuterium Annealing Duration on MOSFET Performance", Semicond. Sci. Technol., vol. 40, no. 11, pp. 1-6, Nov. 2025. [ Website ]
[1] T.-H. Kil, J.-W. Yeon, H.-J. Park, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-M. Kang, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for HfO2 /SiO2 Gate Dielectric in Silicon MOSFETs", IEEE J. Electron Devices Soc., vol. 12, no. 1, pp. 1030-1033, Dec. 2024. [ Website ]
Domestic Journal Papers (KCI)
[1] S.-M. Kang, Y.-J. Choi, H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, M.-S. Kim*, and J.-Y. Park*, "Study on Multiple Post-Metallization Annealing for Enhancing the Performance and Reliability of Silicon MOSFETs", Trans. Electr. Electron. Mater., vol. 38, no. 2, pp. 187–192, Mar. 2025. [ Website ]
Patents
[2] J.-Y. Park, E.-C. Yun, M.-W. Kim, S.-M. Kang, "Rapid Low-Temperature Deuterium Annealing System Including a Reactor Chamber.", KR 10-2025-0064149, May. 2025
[1] J.-Y. Park, J.-W. Yeon, T.-H. Kil, H.-J. Park, Y.-J. Choi, S.-M. Kang, H.-S. Jee, " Low-temperature deuterium annealing method for improving the surface roughness and uniformity of thin films and the semiconductor device manufactured by this method.", KR 10-2024-0053442, Apr. 2024
Conferences
[18] S.-M. Kang, D.-E. Bang, D. Sohn, H.-J. Park, E.-C. Yun, M.-W. Kim, M.-S. Kim, and J.-Y. Park*, "Multi-Level Cell Physically Unclonable Function (PUF) Based on Dual Physical Parameters in Silicon MOSFETs", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[17] D. Sohn, S.-M. Kang, D.-E. Bang, E.-C. Yun, M.-K. Lee, H.-J. Park, M.-W. Kim, and J.-Y. Park*, "DRAM Cell Transistor with Wrap-Around Word-Line (WAW) Structure for Enhancing Read/Write Performance", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[16] M.-W. Kim, H.-J. Park, E.-C. Yun, S.-M. Kang, D.-E. Bang, D. Sohn, and J.-Y. Park*, "Comparative Study of Multiple High-Pressure Rapid Deuterium Annealing for MOSFET Performance Enhancement", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[15] M.-W. Kim, H.-J. Park, E.-C. Yun, S.-M. Kang, D.-E. Bang, D. Sohn, and J.-Y. Park*, "Study on the Efficiency of Deuterium Annealing for Various Process Durations", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[14] D. Sohn, S.-M. Kang, D.-E. Bang, E.-C. Yun, M.-K. Lee, H.-J. Park, M.-W. Kim, and J.-Y. Park*, "DRAM Cell Transistor with Wrap-Around Word-Line (WAW) Structure for Enhancing Read/Write Performance", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[13] S.-M. Kang, D.-E. Bang, D. Sohn, H.-J. Park, E.-C. Yun, M.-W. Kim, M.-S. Kim, and J.-Y. Park*, "Multi-Level Cell Physically Unclonable Function (PUF) Based on Dual Physical Parameters in Silicon MOSFETs", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[12] M.-W. Kim, H.-J. Park, E.-C. Yun, S.-M. Kang, D.-E. Bang, D. Sohn, and J.-Y. Park*, "Comparative Study of Multiple High-Pressure Rapid Deuterium Annealing for MOSFET Performance Enhancement", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[11] M.-W. Kim, H.-J. Park, E.-C. Yun, S.-M. Kang, D.-E. Bang, D. Sohn, and J.-Y. Park*, "Study on the Efficiency of Deuterium Annealing for Various Process Durations", The 33rd Korean Conference on Semiconductors, Jan. 2026. [ PDF ]
[10] J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, D.-E. Bang, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for Improved Immunity against Hot-Carrier Injection in HKMG MOSFETs", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[9] M.-K. Lee, H.-J. Park, E.-C. Yun, J.-W. Yeon, T.-H. Kil, M.-W. Kim, S.-J. Jeon, D.-E. Bang, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Partial Trench Gate Nanosheet FETs for Enhanced ION/ IOFF Ratio", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[8] D.-E. Bang, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Junction Depth Engineered Trench Gate Nanosheet FETs for Suppressing Leakage Current in Parasitic Substrate Channels", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[7] A-Y. Kim, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, D.-E. Bang, S.-M. Kang, and J.-Y. Park*, "Hetero-Gate Dielectric Structures for Reducing Ambipolar Current in Nanosheet Tunneling FETs", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[6] T.-H. Kil, J.-W. Yeon, H.-J. Park, D.-E. Bang, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park*, "Material Engineering of Inner Spacer in Nanosheet FETs to Reduce Off-State Current", The 32nd Korean Conference on Semiconductors, Feb. 2025. [ PDF ]
[5] E.-C. Yun, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, H.-S. Jee, D. Sohn, S.-M. Kang, A-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park*, "Spacer-Less Trench Gate Nanosheet FET for Improved On-State Current and Simplified Fabrication Process", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]
[4] T.-H. Kil, H.-J. Park, J.-W. Yeon, E.-C. Yun, M.-K. Lee, D. Sohn, H.-S. Jee, S.-M. Kang, A-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park*, "Low-Temperature Deuterium Annealing for Enhanced Ionizing Radiation and Electrical Stress Immunity in MOSFETs", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ]
[3] H.-S. Jee, D. Sohn, J.-W. Yeon, H.-J. Park, T.-H. Kil, E.-C. Yun, M.-K. Lee, S.-M. Kang, A-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park*, "Development of Physically Unclonable Function (PUF) using Multiple Process Variables", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ] "Award" [ PDF ]
[2] Y.-J. Choi, S.-M. Kang, H.-J. Park, T.-H. Kil, J.-W. Yeon, H.-S. Jee, E.-C. Yun, M.-K. Lee, D. Sohn, D.-E. Bang, A-Y. Kim, and J.-Y. Park*, "Impact of Hydrogen Passivation after Deuterium Annealing in the Fabrication of Silicon MOSFETs", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ] "Award" [ PDF ]
[1] D.-E. Bang, A-Y. Kim, Y.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, D. Sohn, H.-S. Jee, S.-M. Kang, Y.-J. Choi, and J.-Y. Park*, "Optimization of Doping Profile for Improved Performance of Nanosheet FET", KIEEME Annual Summer Conference 2024, Jun. 2024. [ PDF ] "Award" [ PDF ]
Research Projects
[4] Principal Investigator, Cost-Effective Physically Unclonable Function Using Dual-Parameter Variability in Silicon MOSFETs, National Research Foundation of Korea, Sep. 2025 – Aug. 2026
[3] Research Assistant, Preliminary Study on Structure and Process Development of SiC/GaN/Si Power Devices, ITNC Co., Ltd., Nov. 2025 – Oct. 2026
[2] Research Assistant, Improvement of Gate Dielectric Reliability in Silicon MOSFETs through High-Pressure Deuterium Annealing, Samsung Electronics, Dec. 2024 – Apr. 2025
[1] Research Assistant, Development of Deuterium-Based Semiconductor Process Technology and Services, Ministry of Science and ICT, May. 2024 – Dec. 2024
Teaching Assistant (TA)
[1] Semiconductor Device Fabrication Laboratory, Sep. 2025 – Dec. 2025
Awards
[2] Encouragement Award, Korean Institute of Electrical and Electronic Materials Engineers, 2024
[1] Encouragement Award, Campus Patent Universiade (Hosted by the Korean Intellectual Property Office), 2023 [PDF]