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Memristor based logic circuits

Neuromorphic systems based on memristor crossbar arrays.

More than memory applications, the two-terminal devices can readily form desirable network structures in the form of crossbar arrays, where arrays of column and row electrodes cross each other with one memristive device formed at each cross point. In this physical network structure, memory is stored as different resistance values at the crosspoints. In the meantime, by controlling the resistance at the crosspoints one also directly regulates information (i.e. current) flow between the electrodes. In this sense, the system performs memory and logic functions at the same physical locations, and data do not have to be moved between separate logic and memory units. This approach is an ideal platform to implement network-based machine learning and neuromorphic computing algorithms. For example, analog memristive devices are excellent candidates for implementing synaptic functions in biology-inspired neuromorphic circuits, which can potentially process complex tasks orders of magnitudes more efficiently than conventional circuits. We were the first to demonstrate that solid-state memristive devices can implement biological learning rules such as Spike Timing Dependent Plasticity (STDP) (Jo Nano Lett. 2010). This work has been highlighted in Nature, EE-Times, New Scientists, Chemistry World, PhysOrg, Science Daily, and numerous other print and online news outlets, and has been cited over 1000 times. In subsequent studies, we have demonstrated other functions such as short-term memory to long-term transitions (Chang ACS Nano 2011), and succeeded in integrating high-density memristor arrays (32x32) directly over 180nm and 90nm CMOS logic components (Kim Nano Lett. 2012), including an undergraduate student-led project that shows competition effects in memristor networks (Hermiz APL 2013). Recently, we focused on implementing a mathematically proven algorithm in hybrid memristor/CMOS circuits for energy efficient and high-speed image processing, where the memristor arrays can be used to implement on-line learning and efficient pattern matching functions for low-power and high-throughput analysis for “big data” tasks, 

Bio-realistic emulation and hybrid memristor/bio systems. 

We have recently show that the internal ionic dynamics allow oxide-based memristors to natively emulate internal synaptic dynamic process which naturally leads to different synaptic responses at different stimulation conditions (Kim Nano Lett. 2015, Du Adv. Func. Mater. 2015). We believe this approach can not only lead to efficient computing hardware, but may also be used to study the rich dynamics behavior in biological and man-made networks. Currently we are optimizing the device structure to fine-tune the relevant time-scales in the different dynamic processes, with plans to extend the studies to memristor networks. Additionally, the internal memristor dynamics allow biological signals to be directly and efficiently encoded in hardware, stored, and read out (with the option of being re-programmed in hardware) later and fed back to the biological system in a closed-loop fashion. 

RRAM-based efficient in-memory computing systems. 

Besides neuromorphic computing system based on analog memristor devices, which rely on “soft” computing algorithms where inaccuracy can be tolerated, the two-terminal devices can also be used to efficiently implement the other class of computing tasks – arithmetic computing where accurate computation is needed. Specifically, the crossbar structure allows memory and logic functions to be implemented at the same physical locations, thus avoiding having to moving large amounts of data around and the so-called von Neumann bottleneck.  In this case, we show that universal functions can be implemented in the crossbar arrays through NAND operations based on resistance changes in the devices. More importantly, the high-density array can store all input/output scenarios for a given function, so after the initial programming phase, computing involves simply reading out an output for a given input. Through detailed simulation, we have shown such a system can effectively implement general logic functions with both energy and speed gains compared with conventional digital computers. We are currently working on hardware implementation of this approach. 
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