Xilinx Vivado - Setup/Startup

Do Not Follow these instructions. These are reference instructions for an older design flow. As of Spring 2018 follow the instructions for C9 IDE.

This page illustrates starting up the design environment using the Xilinx Vivado Integrated Development Tool (IDT) and how to maneuver to the design templates you will be provided for your labs.

When you first start Vivado from the X2Go application, you will see the following start up window. I recommend that you always maximize this main ISE window to take advantage of your screen resolution (note red circle below).

Opening a Project

Next press the Open Project button.

In the Open Project window, select your home directory:
 then go down the xilinx/lab<X> path, and select lab<X>.xpr, which is the project file for lab<x> as shown:

The main window will appear with the lab<X> project opened:

Design Views

There are two views and steps to your design: Simulation and Synthesis. Both are visible in this window. The files for both steps are shown in the Sources window, with the file tree expanded with the expand view button circled in red below.
The upper part of the file tree is called Design Sources (scrolled out of view in the above image) which show the Synthesis part of the design. The lower part of the tree shows the Simulation Sources which show the Simulation hierarchy of the design. In the design shown, the module gates is wrapped by a testbench module called tb_gates. Module tb_gates is not synthesizable into hardware, so it is only in the Simulation view. The text vector file, tb_gates.txt is also only in the simulation hierarchy.

Similarly, at the Design Sources part of the tree, there is a top level i/o module that describes the connection the top level signals of module gates to the i/o of the device. In the case of Lab 1 it is called lab1_top_io_wrapper. This module is part of the synthesis tree (Design Sources), and is not in the Simulation Sources part of the tree.

The internal design module, gates, is duplicated in both of the trees, as it is obviously used for both synthesis and simulation.

You open an editor for these Verilog modules (filenames with .v extension) by double clicking on their name in the hierarchical tree. An editing window opens to the right of the Sources window. If you are editing a module that is part of both hierarchies (for example, gates.v), the changes are made to both hierarchies, as it is a single file that is shared.

The editing window is relatively intuitive if you have used programming GUI's in the past.

After you have edited your design, you should save the files, then simulate your design to see if it meets the specifications. When it passes, you then synthesize your design to create a bit file for loading into your hardware. The instructions for each of these steps is provided in separate web pages.

Next: Simulation.