SEMI 3D1-0912Terminology for Through Silicon via Geometrical MetrologyPurchase/Download
Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services. The purpose of this Document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV).Purchase/Download
Specification for Glass Carrier Wafers for 3DS-IC Applications
This Specification describes:
- dimensional, thermal, and wafer preparation characteristics for glass starting material that will be used as carrier wafers in a temporary bonded state;
- glass carrier wafers with nominal diameters of 200 and 300 mm, and a thickness of 700 nm, although the wafer diameter and thickness required may vary due to process and functional variation. Such variations shall be clarified in the purchasing order or in the contract.
Methods of measurements suitable for determining the characteristics in the specifications are indicated.
Guide for Multi-Wafer Transport and Storage Containers for 300 mm, Thin Silicon Wafers on Tape Frames
This Guide is intended to address the needs for choosing a method for shipping thin wafers on tape frames in such a way that they arrive undamaged at their final destination. It describes various methods of shipping thin wafers on tape frames.
Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks
- Control of parameters, such as bonded wafer stack (BWS) thickness, total thickness variation (TTV), bow, warp/sori, and flatness metrology, is essential to successful implementation of a wafer bonding process. These parameters provide meaningful information about the quality of the wafer thinning process (if used), the uniformity of the bonding process, and the amount of deformation induced to the wafer stack by the bonding process.
- This Guide provides a description of tools that can be used to determine these key parameters before, during, and after the process steps involved in wafer bonding.
Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures
This Guide aims to assist in the selection and use of tools for performing measurements of geometrical parameters of an individual TSV (through-silicon via), or of an array of TSVs.
Guide for CMP and Micro-Bump Processes for Frontside Through Silicon Via (TSV) Integration
- proposes a frontside TSV integration scheme as one of the generic middle-end process flow. The flow includes steps such as TSV formation, RDL formation, CMP, temporary carrier bonding, wafer thinning, micro-bump formation, and carrier debonding.
- defines acceptable CMP criteria of TSV in terms of dishing, erosion, and voids. CMP criteria can be determined by metrology technology in both contact methods such as: micro profilometer; 4-points resistivity probes; or non-contact methods (e.g., ultrasonic scan mapping, Coherence Interferometry, or other laser-based light scattering detection schemes). TSV formation and reveal are significantly dependent on the performance of CMP process. The outcome of the high CMP quality yields better TSV connectivity.
- provides criteria for measurement methodology for micro-bump dimensions, including sampling rate, sampling sites and mapping, reference datum, and survey available metrology tools. The outcome will be an important bridge communication among IC design firms, fabs, and packaging houses. The assumption of wafer-to-wafer (W2W), chip-to-wafer (C2W) and chip-to-chip (C2C) are that testing data is available for known test good die.
Guide for Alignment Mark for 3DS-IC Process
This Guide provides the alignment mark strategy for chip to chip, chip to wafer, and wafer to wafer stacking. This Guide also addresses the universal alignment mark where the outcome will be a feasible photo alignment standard.