Department of Electrical and Computer Engineering
3066 Engineering Building II
890 Oval Drive
Raleigh, NC 27606
Dr. James Tuck is an Assistant Professor in the Department of Electrical and Computer Engineering at North Carolina State University and has been since August 2007. He received his Ph.D. from the University of Illinois Urbana-Champaign in Computer Science in 2007 and an MS in Electrical Engineering from the same institution in 2004. He graduated from Vanderbilt University, summa cum laude, with a BE in Computer Engineering in 1999. His research is focused on the design of multicore processor architectures with a focus on hardware/software interactions. As a result, he routinely co-designs processor architectures along with new compiler passes to exploit important cross-layer synergies that help make software or programmers work more efficiently. Dr. Tuck has won two IEEE Micro Top Picks paper awards for his work on multicore processor design. He has published over 20 scientific articles in peer-reviewed computer architecture related conferences, journals, and workshops. He has served on the technical program committee for top conferences in computer architecture and compiler design. Also, his research is sponsored by the National Science Foundation.
- Exploring Helper Computing Parallelism on Multicore Architectures. Supported by NSF CNS-0834664
- Software Exposed Hardware Signatures for Code Analysis, Optimization, and Debugging. Supported by NSF CCF-0952832.
- Compiler and Hardware Support for Thread-Level Speculation
- Reconsidering the Hardware/software Interface in the Multicore Era. Supported by DARPA-PERFECT Program.
- Multicore Architectures in the Dark Silicon Era
- Programmer Aided Optimization and Parallelization. Partially supported by DARPA-PERFECT Program.
- Parallelization of Plant Systems Biology and Engineering Workloads. Supported by NSF INSPIRE-1247427.
Courses taught in the last 5 years:
- ECE 209: Introduction to Computer Systems Programming, every Spring semester since 2008
- ECE 466/566: Code Generation and Optimization, every Fall Semester since 2008
- ECE 803: Computer Architecture Seminar Series, Fall 2008, Fall 2011
NSF/TCPP Early Adopters Participant, Spring 2012
- Rami Al Sheikh, James Tuck, Eric Rotenberg. Control-Flow Decoupling. To appear in MICRO'12: International Symposium on Microarchitecture (MICRO), December 2012.
- Liang Han, Xiaowei Jiang, Wei Liu, Yofeng Wu, and James Tuck. HiRe: Using Hint & Release to Improve Synchronization between Speculative Threads. To appear at the International Conference on Supercomputing (ICS 2012), July 2012. (pdf)
- Rajesh Vanka and James Tuck. Efficient Data Dependence Profiling Using Software Signatures, International Symposium on Code Generation and Optimization, April 2012. (pdf)
- George Patsilaras, Niket K. Choudhar, James Tuck. Exploiting Asymmetric Coupled Cores for Memory Level Parallelism in the Dark Silicon Era. HiPEAC '12, Jan 2012. (pdf)
- Sanghoon Lee and James Tuck. Automatic Parallelization of Fine-grained Meta-functions on a Chip Multiprocessor. CGO'11: IEEE/ACM International Symposium on Code Generation and Optimization, April 2011. (pdf)
- Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tuck. HAQu: Hardware Accelerated Queueing For Fine-Grained Threading on a Chip Multiprocessor. HPCA-17: Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture, February 2011. (pdf)
- Devesh Tiwari, James Tuck, Yan Solihin. MMT: Exploiting Fine Grained Parallelism in Dynamic Memory Management, Proc. of 24th International Parallel & Distributed Processing Symposium (IPDPS) Track-Software, April 2010.
- Liang Han, Wei Liu, James Tuck. Speculative Parallelization of Partial Reduction Variables, CGO'10: IEEE/ACM International Symposium on Code Generation and Optimization, 2010. (pdf) (ppt)
- James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas. Software-Exposed Hardware Signatures for Code Analysis and Optimization. IEEE Micro Magazine Top Picks, 2009. (Originally appeared in ASPLOS'08)
- Luis Ceze, James Tuck, Pablo Montesinos, and Josep Torrellas . Bulk Enforcement of Sequential Consistency. ISCA'07: International Symposium on Computer Architecture, June 2007.
- James Tuck, Luis Ceze, and Josep Torrellas. Scalable Cache Miss Handling for High Memory Level Parallelism. MICRO'06: International Symposium on Microarchitecture (MICRO), December 2006.
- Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau and Josep Torrellas . POSH: A TLS Compiler that Exploits Program Structure. PPoPP'06: Principles and Practice of Parallel Programming (PPoPP), March 2006.
- Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas. Energy-Efficient Thread-Level Speculation on a CMP. IEEE Micro Magazine Top Picks, January-February 2006.
Students who have finished, degree earned, and location of their first job:
- Liang Han, PhD. December 2011 (QualComm, San Diego, CA)
- Sang Hoon Lee, PhD. May 2012 (QualComm, Morrisville, NC)
- George Patsilaras, PhD. May 2012 (QualComm, San Diego, CA)
- Ying Yu, MS, August 2012 (VMWare, San Jose, CA)
- Joonmoo Huh, MS. July 2012 (Continuing PhD student)
Current students and degree sought:
- Rajesh Vanka (PhD)
- Joonmoo Huh (PhD)
- Sid Sharma (MS)
- Jeff Danis, Summer NSF Research Experience for Undergraduates
High School Senior Projects:
- Priyanka Joshi, 2011. A Facebook Application for Predicting the Emotional State of Users
International Symposium on Code Generation and Optimization, 2013
International Symposium on Computer Architecture, 2012
International Symposium on Workload Analysis and Characterization, 2010
International Conference on Parallel Architectures and Compiler Techniques, 2009
HiPEAC External Reviewer, 2013
PESPMA Workshop, in Conjunction with ISCA, 2010, 2009, 2008.
International Symposium on High Performance Computer Architecture, 2009
ABET Committee, Fall '08 until Spring'11
CCC Committee, Spring '11-until now