James Tuck

Associate Professor
Department of Electrical and Computer Engineering
3066 Engineering Building II 
890 Oval Drive
Raleigh, NC 27606

Phone: 919-513-0923
Fax:     919-515-5523
Email:  jtuck -at- ncsu.edu

Useful Links


Dr. James Tuck is an Associate Professor in the Department of Electrical and Computer Engineering at North Carolina State University.  He joined the department in August 2007 as an Assistant Professor.   He received his Ph.D. from the University of Illinois Urbana-Champaign in Computer Science in 2007 and an MS in Electrical Engineering from the same institution in 2004.  He graduated from Vanderbilt University, summa cum laude, with a BE in Computer Engineering in 1999.   His research is focused on the design of multicore processor architectures with a focus on hardware/software interactions.  As a result, he routinely co-designs processor architectures along with new compiler passes to exploit important cross-layer synergies that help make software or programmers work more efficiently.  Dr. Tuck has won two IEEE Micro Top Picks paper awards for his work on multicore processor design.  He has served on the organizing and program committees for top conferences in computer architecture and compiler design. Also, his research is or has been sponsored by the National Science Foundation, DARPA, and Qualcomm.

Research Projects

  • Architectural and Programmer Support for Persistent Memory. Supported by NSF.
  • Cross-Layer Resilience. Supported by NSF and SRC.
  • Data Dependence Profiling and Speculative Optimization. Supported by NSF.
  • Parallelization of Plant Systems Biology and Engineering Workloads. Supported by NSF INSPIRE-1247427.
  • Processing Near Storage. 
  • Parallelization and Vectorization.
  • Multicore Architectures in the Dark Silicon Era
  • Exploring Helper Computing Parallelism on Multicore Architectures. Supported by NSF CNS-0834664
  • Software Exposed Hardware Signatures for Code Analysis, Optimization, and Debugging. Supported by NSF CCF-0952832.
  • Compiler and Hardware Support for Thread-Level Speculation
  • Programmer Aided Optimization and Parallelization. 
  • Reconsidering the Hardware/Software Interface in the Multicore Era.


Courses taught in the last 5 years:
  • ECE 209: Introduction to Computer Systems Programming, every Spring semester since 2008
  • ECE 466/566: Compiler Optimization and Scheduling, every Fall Semester since 2008
  • ECE 803: Computer Architecture Seminar Series, Fall 2008, Fall 2011
NSF/TCPP Early Adopters Participant, Spring 2012

Selected Publications

  • Abhinav Agrawal, Gabe Loh, James Tuck. Leveraging Near-Data Processing for High-Performance Checkpoint/Restart. SuperComputing'17: The ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis 2017, Denver, CO.
  • [Best Paper Runner-up] Tiancong Wang, Sakthikumaran Sambasivam, Yan Solihin and James Tuck. Hardware Supported Persistent Object Address Translation. IEEE/ACM International Symposium on Microarchitecture (MICRO-50), Oct. 14-18, Boston, MA.
  • Seunghee Shin, Satish Kumar Tirukkovalluri, James Tuck and Yan Solihin. Proteus: A Flexible and Fast Software Supported Hardware Logging approach for NVM. IEEE/ACM International Symposium on Microarchitecture (MICRO-50), Oct. 14-18, Boston, MA.
  • Joonmoo Huh and James Tuck. Improving the Effectiveness of Searching for Isomorphic Chains in Superword Level Parallelism. IEEE/ACM International Symposium on Microarchitecture (MICRO-50), Oct. 14-18, Boston, MA.
  • Bagus Wibowo, Abhinav Agrawal, James Tuck. Characterizing the Impact of Soft Errors Across Microarchitectural Structures and Implications for Predictability. IISWC, October 2017. (pdf)
  • Hussein Elnawawy, Mohammad Alshboul, James Tuck, and Yan Solihin. Efficient Checkpointing of Loop-Based Codes for Non-Volatile Main Memory. IEEE/ACM International Conference on Parallel Architectures and Compiler Techniques (PACT) 2017, Portland, OR.
  • Seunghee Shin, James Tuck, Yan Solihin. Hiding the Long Latency of Persist Barriers Using Speculative Execution.  International Symposium on Computer Architecture, 2017, Toronto, CA.
  • Reed Milewicz, Rajesh Vanka, James Tuck, Dan Quinlan, Peter Pirkelbauer.  Runtime Checking C Programs. ACM Symposium on Applied Computing, Programming Languages Track, April 2015.
  • Bagus Wibow, Abhinav Agrawal, James Tuck. Toward a Cross-Layer Approach for Dynamic Vulnerability Estimation.  IEEE SELSE Workshop, 2014.
  • Rami Al Sheikh, James Tuck, Eric Rotenberg. Control-Flow Decoupling.  To appear in MICRO'12: International Symposium on Microarchitecture (MICRO), December 2012. (pdf)
  • Liang Han,  Xiaowei Jiang, Wei Liu, Yofeng Wu, and James Tuck. HiRe: Using Hint & Release to Improve Synchronization between Speculative Threads. To appear at the International Conference on Supercomputing (ICS 2012), July 2012. (ACM DL)
  • Rajesh Vanka and James Tuck.  Efficient Data Dependence Profiling Using Software Signatures, International Symposium on Code Generation and Optimization, April 2012. (pdf)
  • George Patsilaras, Niket K. Choudhar, James Tuck. Exploiting Asymmetric Coupled Cores for Memory Level Parallelism in the Dark Silicon Era. HiPEAC '12, Jan 2012. (pdf)
  • Sanghoon Lee and James Tuck.  Automatic Parallelization of Fine-grained Meta-functions on a Chip MultiprocessorCGO'11: IEEE/ACM International Symposium on Code Generation and Optimization, April 2011. (pdf)
  • Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tuck.  HAQu: Hardware Accelerated Queueing For Fine-Grained Threading on a Chip Multiprocessor.   HPCA-17: Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture, February 2011. (pdf)
  • Devesh Tiwari, James Tuck, Yan Solihin. MMT: Exploiting Fine Grained Parallelism in Dynamic Memory Management, Proc. of  24th International Parallel & Distributed Processing Symposium (IPDPS) Track-Software, April 2010.
  • Liang Han, Wei Liu, James Tuck.  Speculative Parallelization of Partial Reduction VariablesCGO'10: IEEE/ACM International Symposium on Code Generation and Optimization, 2010. (pdf) (ppt)
  • James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas.  Software-Exposed Hardware Signatures for Code Analysis and Optimization. IEEE Micro Magazine Top Picks, 2009. (Originally appeared in ASPLOS'08)
  • Luis Ceze, James Tuck, Pablo Montesinos, and Josep Torrellas . Bulk Enforcement of Sequential Consistency. ISCA'07: International Symposium on Computer Architecture, June 2007.
  • James Tuck, Luis Ceze, and Josep Torrellas. Scalable Cache Miss Handling for High Memory Level ParallelismMICRO'06: International Symposium on Microarchitecture (MICRO), December 2006.
  • Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau and Josep Torrellas . POSH: A TLS Compiler that Exploits Program StructurePPoPP'06: Principles and Practice of Parallel Programming (PPoPP), March 2006.
  • Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas. Energy-Efficient Thread-Level Speculation on a CMP. IEEE Micro Magazine Top Picks, January-February 2006.

Mentored Students

Students who have finished, degree earned, and location of their first job:
  • Liang Han, PhD. December 2011 (QualComm, San Diego, CA)
  • Sang Hoon Lee, PhD. May 2012 (QualComm, Morrisville, NC)
  • George Patsilaras, PhD.  May 2012 (QualComm, San Diego, CA)
  • Ying Yu, MS, August 2012 (VMWare, San Jose, CA)
  • Joonmoo Huh, MS. July 2012 (Continuing PhD student)
  • Rajesh Vanka, PhD. May 2013 (MathWorks, Boston, MA)
  • Sid Sharma, MS.  May 2014. (NVidia)
  • David Mabe, MS. May 2015. (Synopsis, NC)
  • Apoorv Parle, MS. May 2016. (Intel, CA)
  • Laxman Sole, MS. June 2017. 
Current students and degree sought:
  • Bagus Wibowo (PhD)
  • Abhinav Agrawal (PhD)
  • Joonmoo Huh (PhD)
  • Tiancong Wang (PhD)
  • Alexander Simpson (PhD)
Undergraduate Research:
  • Lingxiao Zheng, REU Data Dependence Profiler
  • Thomas Stanton, REU Cross-layer Resilience
  • Jeff Danis, Summer NSF Research Experience for Undergraduates
High School Senior Projects:
  • Priyanka Joshi, 2011.  A Facebook Application for Predicting the Emotional State of Users

Program Committees

International Symposium on Code Generation and Optimization (CGO), 2013, 2014, 2015.
International Symposium on Computer Architecture (ISCA), 2012
International Symposium on Workload Analysis and Characterization (IISWC), 2010
International Conference on Parallel Architectures and Compiler Techniques (PACT), 2009
HiPEAC External Reviewer, 2013-2017
PESPMA Workshop, in Conjunction with  ISCA, 2010, 2009, 2008.

Organizing Committees

ASPLOS General Co-Chair, 2018
LCPC General Co-Chair, 2015
Local Arrangements Chair, ISWC, 2014
Student Travel Chair, ISCA 2014, 2015
Finance Chair, CGO 2014
Local Arrangements Chair, ICCD 2013
Publicity Chair, HPCA, 2009

Departmental Committees

CCC Committee,  Spring '11-until now
ABET Committee, Fall '08 until Spring'11