Our current HPC ecosystem relies upon Commercial off-the-Shelf (COTS) building blocks to enable cost-effective design by sharing costs across a larger ecosystem. Modern HPC nodes use commodity chipsets and processor chips integrated together on custom motherboards. We are embarking upon a new era for commodity HPC where the chip acts as the "silicon motherboard" that interconnects commodity Intellectual Property (IP) circuit building blocks to create a complete integrated System-on-a-Chip (SoC). This approach is still very much COTS, but the commodities are licensable IP for pre-verified circuit designs (the lego-blocks for SoC designs) rather than the chips. It achieves cost-competitiveness because the dominant cost of designing a chip is the cost of verifying the circuit building blocks. The cost benefits derive from the ability to leverage a commodity ecosystem of embedded IP logic components where the non-recurring expense (NRE) cost of designing and verifying a new processor or memory controller design (an IP building block) can be amortized by licensing the technology to myriad embedded applications. The market for licensed circuit IP in the embedded space is much larger marketplace (both in volume and total revenue) than for server chips and the market segment for SoC building blocks is growing at a far faster pace than the current server chip market. HPC system designers should leverage this new avenue for leveraging the cost-advantages of COTS technology.
Traditionally SoC design methods have focused on low-power consumer electronics or high performance embedded applications. But now SoC design methods are moving into high-end computing due to the emergence of embedded IP offering capable double-precision floating point, 64-bit address capability, and options for high performance I/O and memory interfaces. The SoC approach enables HPC chip designers to include features they need, and exclude features that are not required in a manner that is not feasible with today's commodity board-level computing system design. System on Chip (SoC) integration is able to further reduce power, increase integration density, and improve reliability. It also enables designers to minimize off-chip I/O by integrating peripheral functions, such as network interfaces and memory controllers by integrating the components onto a single chip. Furthermore, the embedded market has developed extraordinarily capable tools for rapidly prototyping, simulating, and synthesizing full SoC designs, with a much faster turn-around than we have come accustomed to for commodity server chip designs (many designs targeted at an 18 month design cycle for the hyper-competitive consumer market). By leveraging the enormous commodity IP market for design tools, processors, memory controllers, and I/O circuit designs, a chip designer can focus their effort and NRE costs on engineering handful of essential features that are not covered by the commodity ecosystem.
This workshop will explore the following questions:
1) State of the Art: What can be done to leverage commodity embedded IP components, tools, and design methodologies to create HPC-targeted designs. We will review the current state-of-the-art SoC design workflow and the key technology components that are currently available on the open market.
2) Technology Inventory and Requirements Analysis: We will survey the currently available IP building blocks and identify where gaps exist in current IP circuit technologies and design tools that will be crucial to HPC and datacenter-targeted SoC ASICS. The NoC fabrics that connect the IP components together does not guarantee a trouble-free SoC design process, and there are many crucial components for HPC that are not available for licensing. In addition, technology integration, such as low cost integration of memory cubes and advanced packaging pose challenges.
3) Software Infrastructure: What will be required of our software environment to take full advantage of a rapidly evolving SoC designs. What would need to change in our software engineering practices keep up with a more flexible and rapidly evolving hardware design target?
4) Simulation/Modeling: SoC poses challenges to existing monolithic CPU-centric simulation environments that were originally designed for cell-phone scale systems. What new technologies will be required to bring the kind of design agility to the HPC-SoC design space that is currently relied upon for competitive consumer electronic designs.
5) OpenSoC: What open technologies, tools, and open-source gate-ware are available to engage the academic and research community involved in exploring the design space for high performance SoCs.
John Shalf, Computer Architecture Lab, Lawrence Berkeley National Laboratory
James Ang, Computer Architecture Lab, Sandia National Laboratories
The HPC-SoC workshop will focus on semi-custom, application-targeted designs, and server processing for HPC and data-centers, with the goal to develop a strategy for an open fabric that is targeted at SoC designs for high end computing applications.
1801 California St., Ste. 2800
Denver, CO 80202
Optional meal fee is $25 per day, which includes lunch, breakfast snacks, coffee, and refreshments.
The Leidos offices are located in downtown Denver four blocks from the Denver Convention Center, with plentiful nearby hotels. For this reason we did not reserve a block of rooms, rather participants can choose from their preferred hotel chain in order to obtain government rates. The estimated cost ranges from a nearby Residence Inn at $156/night to the Denver Marriott Courtyard downtown at $195/night.
Registration: May 20 - June 15
Workshops: August 26, 8:30am - 5:30pm August 27, 8:30am-5:30pm, (Tuesday, Wednesday)
Steering Committee: August 28, 8:30am-12:00pm (Thursday)
Participants confirmed as of 8/13/14
Ang, James SNL
Bergman, Larry NASA/JPL
Harrod, William DOE/SC
Hiller, Jon STA representing DARPA/MTO
Jiang, Hong NSF
Shalf, John LBNL
Wheeler, Noel LPS/ACS