KEC Faculty Profile

Journals Published (International):

A.Vennila V.R.Saraswathy M.Illakia P.Harshikka Devi V. Naagavighnesh 'Automatic Detection of Mismatched Pattern in Punched Cards for Small Scale Power Loom Applications' International Journal of Scientific & Technology Research,2020 Vol.9,Issue 2,pg.415-417.

International conference:

1. V. R. Saraswathy, M. Prabhu Ram, A. Vennila, S. G. Dravid, 'Application of Rough Set Based Reduction for     Network data set' 2018 Intelligent Computing and Communication for Smart World

2. Vennila, A., Balambigai, S., Deepa, G., Ilakkia, M., Devi, P.H. and Naagavignesh, V., 2021, February. Image recognition based billing system for fruit shop using raspberry PI. In IOP Conference Series: Materials Science and Engineering (Vol. 1055, No. 1, p. 012030). IOP Publishing.

National Conference:

       A.Vennila , 'Implementation Of Modified Histogram Bin Shifting Based Reversible Watermarking' National Conference On  MicrowaveAnd          Optical Communication, Karaikudi 2014.

Sponsored seminar organized:

Subjects handled:

UG Courses:

1. Digital Electronics

2. Digital Communication

3. Analog and Digital Communication

4. VLSI design

5. Data Communication and Networking

6. Object Oriented Concepts and Programming with C++

7.Control Engineering

8.Communication Engineering

PG Courses:

1. HDL for IC Design

2. Verilog HDL for Embedded FPGA Processor

3. Electronic Design Automation Tools

4.Advanced Digital System Design

5. Testing of VLSI circuits

Material:

1. Object oriented concepts and programming with C++:

1. basic concepts

2. operator overloading

3. inheritance

4. template and exception handling

5. file

6. template and exception handling- https://drive.google.com/file/d/1Cq3DWobcSq5WpyUSViWBc0LRIPqpPZpc/view?usp=sharing

2. Verilog HDL for embedded FPGA processor:

1. Overview of Digital Design with Verilog HDL- https://drive.google.com/file/d/1GWHjt7tC1ye_IYMgHRbKtBERD7UkD-n8/view?usp=sharing  

2.Hierarchical Modeling Concepts-  https://drive.google.com/file/d/1SGDcgibDbMIY5o-bjRuCjaI5duypMCUE/view?usp=sharing  

3. Basic Concepts in Verilog   https://drive.google.com/file/d/1tn8Dr8SHyJZwfnZJfNDZDlSU0b4qVpk7/view?usp=sharing

4. modules and ports

3. HDL for IC design:

system verilog

BlueSpec System Verilog 

4.Digital electronics:

1. Number system

2. Complements

3. Signed numbers

5.VLSI laboratory:

modelsim

6. VLSI Design:

unit-5: Testing

7. Advanced Digital System Design

FPGA

ALTRA

PLD language

8. Testing of VLSI circuits

Scan architecture