NCTU Parallel Computing System Lab

About Us                                                                                                   

  • Welcome to NCTU Parallel Computing System Lab (PCS Lab). Our research focuses on design and implementation of parallel computing systems. The expertize of the group spans across multiple design layers, including multi-core architecture, parallel task management, parallel applications, system optimization, design framework, and methodology. Research contributions from different aspects will cooperate with each other and become the enablers to a high performance, energy efficient and cost effective parallel computing system.
  • The lab is located at Room 520, Engineering Building D. We currently have several funded projects. 
    • You are more than welcome to contact Professor Lai (ED402) for more information, or simply visit the lab (ED520) and chat with the group members.
  • We are currently looking for:
    • Ph.D. and M.S. students who would like to join a motivated research team, and work on challenging topics of design and optimization of parallel systems.
    • Undergraduate students who would like to accumulate research experiences and work on interesting research projects.
 News                                                                                                           
2017-7 Our work, "An Efficient Hierarchical Banking Structure for Algorithmic Multi-Ported Memory on FPGAs", is accepted by IEEE Transactions on VLSI (TVLSI).
2017-6 品彰 passes his Master Oral Defense. Congratulations!
2017-5 建宇 passes his Master Oral Defense. Congratulations!
2017-5 Our work, "A Software Technique to Enhance Register Utilization of Convolutional Neural Networks (CNNs) on GPGPUs", is accepted by IEEE International Conference on Applied System Innovation.
2017-4 Our work, "A Hadoop-base Principle Component Analysis on Embedded Heterogeneous Platform", is accepted by VLSI-DAT 2017.
2017-1 Our work, "Efficient Designs of Multi-Ported Memory on FPGAs", is accepted by IEEE Transactions on VLSI (TVLSI).
2016-12 Our work, "Unified Designs for High-Performance LDPC Decoding on GPGPUs", is accepted by IEEE Transactions on Computers (TC).
2016-9 子豪 passes his Master Oral Defense. Congratulations!
2016-8 哲懷 passes his Master Oral Defense. Congratulations!
2016-7 琨驊 and 
Moustafa (毛沙敏) passes their Master Oral Defense. Congratulations!
2016-4 Our work, "Scalable Multi-Layer Barrier Synchronization on NoC", is accepted by VLSI-DAT 2016.
2016-4 Our work, "A Quantitative Method To Data Patterns of SIMT Applications", is accepted by IEEE Computer Architecture Letters.
2015-9 Our work, "Design of Application Specific Throughput Processor for Matrix Operations", is accepted by The 18-th International Conference on Network-Based Information Systems (NBiS).
2015-8 柏堯, 于倫, 俊良, 聖諺, and 佳穎 passes their Master Oral Defense. Congratulations!
2015-7 Our work, "Computation and Communication Aware Task Graph Scheduling on Multi-GPU Systems", is accepted by IEEE International Conference on Digital Signal Processing.
2015-4 Our work, "Self Adaptable Multithreaded Object Detection on Embedded Multicore Systems", is accepted bJournal of Parallel and Distributed Computing.
2015-4 Our work, "Power Efficient Instancy Aware DRAMs Scheduling", is accepted by IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences.
2015-4 Our work, "BRAMs efficient multi-ported memory on FPGAs", is accepted by VLSI-DAT 2015.
2014-11 Our work, "Scalable Global Power Management Policy Based-on Combinatorial Optimization for Multiprocessor Systems", is accepted by ACM Transactions on Embedded Computing Systems.
2014-11 Our work, "A Learning-on-Cloud Power Management Policy for Smart Devices", is accepted by IEEE/ACM The International Conference on Computer-Aided Design (ICCAD).
2014-11 Our work, "A High-Performance Double Layer Counting Bloom Filter for Multicore Systems", is accepted by IEEE Transactions on VLSI (TVLSI).
2014-6 秉儒 and 允廷 passes his Master Oral Defense. Congratulations!
2014-6 Our work, "A Cache Aware Multithreading Decision Scheme on GPGPUs", is accepted by The 8th IEEE 8th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip (MCSoC-14).
2014-6 Our work, "Automatic Data Layout Transformation for Heterogeneous Many-core Systems", is accepted by the 11th IFIP International Conference on Network and Parallel Computing.
2014-5 Our work, "Reducing Contention in Shared Last-Level Cache for Throughput Processors", is accepted by ACM Transactions on Design Automation of Electronic Systems.
2014-5 玹凱 passes his Ph.D. Oral Defense. Congratulations!
2014-4 坤駿 passes his Master Oral Defense. Congratulations!
2014-3 智恆 and 大剛 passes their Master Oral Defense. Congratulations!
2014-1 Our work, "A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs", is accepted by IEEE Transactions on Computers (TC).
2013-9 Our work, "A Locality-Aware Dynamic Thread Scheduler for GPGPUs", is accepted by PDCAT 2013.
2013-7 奏翰, 柏諺, and Luis (盧以斯) passes their Master Oral Defense. Congratulations!
2013-7 Our work, "Memory Capacity Aware Non-Blocking Data Transfer On GPGPUs", is accepted by SiPs 2013.
2013-7 Our work, "A High-Performance Depth Map Optimization on Heterogeneous Many-core Systems", is accepted by VLSI-CAD 2013.
2013-4 Our work, "A Distributed Thread Scheduler for Dynamic Multithreading on Throughput Processors", is accepted by VLSI-DAT 2013.
2012-12 Our work, "Reduce Data Coherence Cost with An Area Efficient Double Layer Counting Bloom Filter", is accepted by APSIPA 2012.
2012-10 Our Work, "A High-Performance Parallel Graph Cut Optimization For Depth Estimation"is accepted by ICS 2012.
2012-9 冠儒 passes his Master Oral Defense. Congratulations!
2012-9  Our Work, "Cache Capacity Aware Thread Scheduling for Irregular Memory Access on Many-Core GPGPUs"is accepted by ASPDAC 2013.
2012-9  Our Work, "Reduce Data Coherence Cost with An Area Efficient Double Layer Counting Bloom Filter"is accepted by PAAP 2012.
2012-9  Our Work, "A Highly Parallel Design for Irregular LDPC Decoding on GPGPUs"is accepted by APSIPA 2012.
2012-1  Our Work, "A Highly Parallel Design of Image Surface Layout Recovering on GPGPUs", is accepted by VLSI-DAT 2012.
2011-9  彥凱 received an "Outstanding Achievement Award" on the Altera Design Contest (ADC) 2011
2011-9  Our work, "Thread Affinity Mapping for Irregular Data Access on Shared Cache GPGPUs", is accepted by ASP-DAC 2012.
2011-9  彥凱 project goes into the final of Altera Design Contest (ADC) 2011. 
2011-9  奏翰 and 冠儒 receive the outstanding "TA awards" for their endeavors to the teaching on Logic Design in spring 2011.
2011-9  Our work on Multi-threaded Object Detection Algorithm is accepted by ICPADS 2011.
2011-8  琬菁 and 志軒 passes their Master Oral Defense. Congratulations!
2011-7 Our work, "Data Locality Optimization for A Parallel Object Detection On Embedded Multi-Core Systems", is presented on ICSESS 2011.
2011-1  Our work, "Multi-Level Parallelism Analysis of Face Detection on a Shared Memory Multi-Core Systems", is accepted by VLSI-DAT 2011.
2011-1  Our work, "FDPrior: A Force-Directed Based Parallel Partitioning Algorithm for Three Dimensional Integrated Circuits on GPGPUs", is accepted by VLSI-DAT 2011.