Jink as designed to assist in and orchestrate the HW/SW design flows in the ENOSYS project. The tool simplifies tedious SoC customization and implementation processes and drives all the ENOSYS tools.
Jink links together Modelio, the ENOSYS design entry tool, ACOT, the source-to-source transformation tool, the LE1 toolchain and the PSoC infrastructure. The latter includes all Xilinx IP and toolchains and the LE1 RTL. The tool drives the whole ENOSYS flow and produces a final bitstream which is downloaded on the FPGA development board (Xilinx ML605 board).
For downloading JINK, LE1 tool set or any other questions, suggestions, bug reports, etc. please contact: V.Chouliaras@lboro.ac.uk
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