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Hardware Interface

The RIFFA channel has several ports that are used for signaling between the PC and the FPGA. We've tried to keep it as simple and flexible as possible.

The RIFFA interface is a collection of ports for signaling data transfer, requesting buffers, and signaling events. The table below describes the ports. The input/output designations are from the IP core's perspective.
 Name I/O Description
 INTERRUPT O  Assert high to signal an interrupt to the PC on the channel.
 INTERRUPT_ERR O  Assert high to signal an error with the interrupt. Only valid/used when INTERRUPT is high.
 INTERRUPT_ACK I  Pulsed high after the INTERRUPT has been received.
 DOORBELL I  Pulsed high when PC sends a doorbell to the IP core.
 DOORBELL_ERR I  If high when DOORBELL is pulsed, indicates an error signal with the doorbell.
 DOORBELL_LEN I  If non-zero, indicates the amount of data received in the IP core's buffer (from the PC).
 DOORBELL_ARG I  Contains a "function call" style 32 bit argument of data. Asserted after DOORBELL's pulse.
 DMA_REQ O  Assert high to request a DMA transfer.
 DMA_REQ_ACK I  Pulsed high when DMA request has been received.
 DMA_SRC O  The system bus starting address of the transfer source. Must be valid when DMA_REQ is asserted.
 DMA_DST O  The system bus starting address of the transfer destination (sink). Must be valid when DMA_REQ is asserted.
 DMA_LEN O  The length of the transfer in bytes.
 DMA_SIG O  If high, the PC on the channel will receive an interrupt after the transfer completes. Only used when DMA_REQ is asserted. 
 DMA_DONE I  Pulsed high when the transfer is complete.
 DMA_ERR I  If high, indicates an error in the transfer. Only used when DMA_DONE is pulsed.
 BUF_REQ O  Assert high to request a PC buffer.
 BUF_REQ_ACK I  Pulsed high when the buffer request has been received.
 BUF_REQ_ADDR I  PC buffer system bus address.
 BUF_REQ_SIZE I  PC buffer size in powers of 2 (e.g. a value of 10 means 2^10 = 1024 bytes).
 BUF_REQ_RDY I  Pulsed when PC buffer information is ready and asserted.
 BUF_REQ_ERR I  If high, indicates an error in receiving the PC buffer information. Only used when BUF_REQ_RDY is pulsed.
 BUF_REQD I  Pulsed high when a buffer is requested from the IP core.
 BUF_REQD_ADDR O  IP core buffer system bus address.
 BUF_REQD_SIZE O  IP core buffer size in powers of 2 (e.g. a value of 10 means 2^10 = 1024 bytes). 
 BUF_REQD_RDY O  Pulse high when the IP core buffer is ready.
 BUF_REQD_ERR O  If high, indicates an error in allocating the IP core buffer. Only used when BUF_REQD_RDY is pulsed.

Below are timing diagrams for common scenarios (again from the perspective of a connected IP core).

Doorbell/Interrupt Timing Diagram

The above diagram show an IP core receiving a data transfer of 8 KB followed by a "start" doorbell signal (zero length). After some processing the IP core issues an interrupt, signaling completion. If the INTERRUPT_ERR port were high when INTERRUPT was asserted, this would signal an error condition for the interrupt. The INTERRUPT port must be asserted and held high until the INTERRUPT_ACK is pulsed. When a doorbell is received, the DOORBELL signal is pulsed at the same time the DOORBELL_LEN is valid. If the DOORBELL_ERR port were high when the DOORBELL port is pulsed, that would indicate an error condition for the doorbell. In the following two cycles, the DOORBELL_ARG port will output the "function call" style 32 bit arguments, arg0 then arg1. This pattern occurs every time a doorbell is received, regardless of whether the length and arg values are non-zero. Note that the arg values outputted are the last arg values specified by the PC. So they may be from previous "function calls".  

DMA Transfer Timing Diagram

The above diagram shows the timing for a DMA transfer from src_addr to dst_addr of 8 KB. The DMA_SRC, DMA_DST, DMA_LEN, and DMA_SIG ports must be valid when the DMA_REQ port is asserted. The DMA_REQ port must be held high until the DMA_REQ_ACK port is pulsed. The DMA_SIG high means that after the transfer is complete, the PC will receive an interrupt containing the length of the transferred data. After the transfer is complete the DMA_DONE port is pulsed. If there was an error during the transfer, the DMA_ERR signal would be high during the DMA_DONE pulse. The DMA_ERR port is only valid when the DMA_DONE is pulsed.

FPGA Buffer Requested Timing Diagram

The diagram above shows the timing for a FPGA buffer request. When the PC transfers data to the FPGA, it requests a FPGA buffer for the destination. This buffer is specified by the IP core on the channel. The IP core must provide a system bus address and a size in terms of powers of 2 (e.g. a value of 11 means 211 = 2048). Each request may be satisfied by the same buffer or different buffers. This is left up to the IP core. In the example above the buffer is specified at address addr with a size of 2048 bytes. As seen earlier, the transfer of data to this buffer (from the PC) will result in a doorbell with the length of the bytes transferred (which will always be <= buffer size). Note that the BUF_REQD port will only be held high for 32 cycles. If the IP core does not provide a response and pulse BUF_REQ_RDY within 32 cycles of BUF_REQD going high, the PC will receive an error condition.

PC Buffer Requested Timing Diagram

The diagram above shows the timing for a PC buffer request. When the FPGA transfers data to the PC, it requests a PC buffer for the destination. This buffer is specified by the PC thread on the channel. The PC must provide a system bus address and a size in terms of powers of 2 (e.g. a value of 11 means 211 = 2048). Each request may be satisfied by the same buffer or different buffers. This is determined by the available buffers on the PC. In the example above, the PC buffer is specified at address addr with a size of 2048 bytes. Similar to the transfer of data from the PC to the FPGA, when data is received in the PC buffer, the PC will receive an interrupt with the length of the bytes transferred (which will always be <= buffer size). The BUF_REQ port must be held high until the BUF_REQ_ACK. There is no bound on the number of cycles between when a PC buffer is requested and when a response will be returned to the IP core. If the PC does not provide a response and pulse BUF_REQ_RDY within a time frame required by the IP core, the IP core should issue an interrupt with an error condition.


The SIMPBUS interface is a simplified address bus protocol that allows components to be ported between specific bus protocols (e.g. Xilinx PLB, AXI, etc.). This interface is also used in the RIFFA framework. The table below describes the ports. The input/output designations correspond to the master arrangement. The slave arrangement is inverted.
 Name I/O Description
 SIMPBUS_ADDR O  Bus address. Should be as wide as the system bus address to which it is connected (32, 64, etc.)
 SIMPBUS_WDATA O  Data to be written to the bus.
 SIMPBUS_RDATA I  Data read from the bus.
 SIMPBUS_BE O  Byte enable for reading and writing from/to the bus.
 SIMPBUS_RNW O  Read not write flag.
 SIMPBUS_START O  Start (active high) level indicator. Must be held high until SIMPBUS_DONE is asserted.
 SIMPBUS_DONE I  Done (active high) level indicator. Will be held high for just 1 cycle.
 SIMPBUS_ERR I  Error (active high) level indicator. Will be held high for just 1 cycle. Only valid when SIMPBUS_DONE is high.

Below are timing diagrams for common scenarios using the SIMPBUS interface.

SIMPBUS Read Timing Diagram

SIMPBUS Write Timing Diagram

In the diagram above on the left, we see a read transaction. Note that the SIMPBUS_START port is held high until the SIMPBUS_DONE port is pulsed. If the SIMPBUS_ERR were high during the SIMPBUS_DONE pulse, this would indicate an error in reading. The SIMPBUS_ADDR, SIMPBUS_BE, and SIMPBUS_RNW should all be valid while the SIMPBUS_START is held high. The SIMPBUS_RDATA is only valid during the SIMPBUS_DONE pulse.
In the diagram on the right, we see a write transaction. Again, notice that the SIMPBUS_START port is held high until the SIMPBUS_DONE port is pulsed. If the SIMPBUS_ERR were high during the SIMPBUS_DONE pulse, this would indicate an error in writing. The SIMPBUS_ADDR, SIMPBUS_BE, SIMPBUS_RNW, and SIMPBUS_WDATA should all be valid while the SIMPBUS_START is held high.