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RIFFA 1.0

RIFFA 1.0 is a Reusable Integration Framework for FPGA Accelerators. It connects IP cores on an FPGA with user software running on a Linux computer to provide high bandwidth, low latency synchronization and communication. The framework requires a PCIe bus enabled workstation and a FPGA with a PCIe peripheral. RIFFA provides communication and synchronization capabilities with a standard interface for both software and hardware. It is comprised of Verilog and VHDL IP cores, C software libraries, and a Linux device driver. Our paper on RIFFA has been published in the 20th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines.

The 1.0 version of RIFFA has been deprecated in favor of the 2.0 version of RIFFA. However, both versions are still freely available and can be downloaded

With RIFFA 1.0, software engineers are presented with a C/C++ API that hides the low level communications details. Engineers can communicate with FPGA IP cores by writing only a few lines of code, as in the example below.

User Application Example

#define DATA_SIZE (8192)

int main(int argc, char* argv[]) {
fpga_dev * fpgaDev;
int recv, channel, timeout;
unsigned int arg0, arg1;
unsigned char data[DATA_SIZE];

timeout = 10*1000; // 10 secs.
channel = 0;
arg0 = (unsigned int)rand(); // Random
arg1 = (unsigned int)rand(); // values

// Initialize the FPGA & open the channel.
fpga_init(&fpgaDev);
fpga_channel_open(fpgaDev, channel, timeout);

// Send 2 arguments to the core on the channel,
// then send a "start" doorbell.
fpga_send_args(fpgaDev, channel, arg0, arg1, 2, 1);

// Receive the response data.
recv = fpga_recv_data(fpgaDev, channel, data, DATA_SIZE);
printf("Received data response, length: 0x%x\n", recv);

// Close the channel and free the device.
fpga_channel_close(fpgaDev, 0);
fpga_free(fpgaDev);

return 0;
}

FPGA designers are provided a simple assert and pulse interface for communicating with software applications. This interface hides the timing and protocol details of communicating over the various buses from the IP core. IP cores are provided with a simple hardware interface for transferring data and sending/receiving signals.

The communications model is based on direct memory access (DMA) transfers and interrupt/doorbell signaling. This achieves high bandwidth over the PCIe connection. In our tests we are able to achieve a sustained transfer rate of 72% of the theoretical PCIe maximum bandwidth. This connection also supports low latency signaling on the order of 1 μs.

We have tested RIFFA on Xilinx FPGA development boards: ML506, ML507, and ML509/XUP5V with a single lane x1 PCIe Gen1 connection. All our designs have been run at 125 MHz. We have used Xilinx tools version 13.3 for most of our work. RIFFA has be tested on Fedora 13 & 17 (32/64 bit vers.) and Ubuntu Desktop 10.04 LTS & 12.04 LTS (32/64 bit vers.). RIFFA relies on a custom Linux kernel driver which is supported on Linux kernels 2.6.27+ (tested on versions between 2.6.32 - 3.3.0).

You can download RIFFA 1.0 now. Please read the release-notes.txt in the distribution as there are some limitations to this release. We welcome feedback and any help to improve the project.