Hardware Accelerated Real time Lane Detection

By Vijay Venkataraman, Janarbek Matai and Prof Ryan Kastner


Many of the image processing algorithms today are being implemented on a microcontroller based system or on a digital signal processor. One of the many reasons for this is the ease of programming in a high level language like C/C++. But with processor based architectures, we hit a roadblock in performance given the limited amount of memory, and fixed clock frequency for synthesis. This restricts real time processing.

The constraint while using FPGA is to program in a HDL like Verilog or VHDL, which is more labor intensive and error prone.

A high level synthesis tool essentially takes input as a C/C++ code and converts it to a HDL code. This can be further synthesized using a tool like Xilinx ISE. Vivado HLS is a tool suite provided by Xilinx which helps us in the entire process of high level synthesis