My Patents


I excel in the development of intellectual property for my employers.  I have 11 patents (10 awarded, 1 pending) in mixed-signal circuit design, semiconductor components, and communication methods.  An overview of these patents is provided below.  Though some of these patents were group efforts, I have specifically described my contributions on this page.

Pending Patents

20090028218   USB system with spread spectrum EMI reduction

By Dan Hariton et al.  -- Filed USPTO 2007 and PCT 2008


This invention applies spread-spectrum EMI reduction to USB 2.0 while maintaining full USB compliance.  This was previously thought impossible by the authors of the USB 2.0 specification.

The diagram to the left shows that spread-spectrum is applied at the source (input frequency or crystal) while the original USB 2.0 ASIC PHY architecture remains compatible with this addition.
Awarded Patents

7,561,002 and 7,679,464   Method and apparatus for frequency modulating a periodic signal of varying duty cycle 

By Dan Hariton et al.  -- Filed 2005 and 2008




This invention reduces the conducted and radiated EMI achieving 9 dB attenuation of the fundamental switching frequency.  This does not require a PLL.  

The diagram to the left shows that the peaks of the fundamental and harmonics without spread spectrum are higher by a factor of 9 dB.

7,676,012 Spread spectrum controllable delay clock buffer with zero cycle slip

By Venugopal Narendar and Dan Hariton et al., Filed 2004




This invention allows complete quantitative control of the fractional or integer cycle slippage under spread spectrum conditions.


6,646,463  Impedance emulator (continued from 6,351,137)

By Dan Hariton -- Filed 2002 



This invention reduces the size of a capacitor by replacing it with an active circuit and a resistance ratio.  This enables manufacturers to save silicon layout area and reduce cost.

Figure 6a (to left) shows the original circuit, which uses a 600 pF capacitor.  Figure 6b is a network transformation (intermediate step).  Figure 6c is the final circuit with a capacitor that is 10 times smaller (60 pF) than the original circuit.

This method is a non-Miller capacitance multiplier.


6,624,405  BIST for testing a current-voltage conversion amplifier
By Anthony Lau and Dan Hariton -- Filed 1999


This invention is a circuit allowing dual input test signals (current and voltage) for an integrated transimpedance amplifier.  This enables more efficient testing of photodiode front-end circuits.

The dual function circuit can be selected between functioning as a current to voltage conversion circuit connected to a photodiode and as a testing circuit for testing the transimpedance amplifier without exposing light to the photodiode.  No switching is required to select between the test mode and the normal mode.




6,104,558 Low noise ESD protection circuit for mixed signal CMOS integrated circuits

By Dan Hariton et al. -- Filed 1998


This invention provides cross-coupled ESD protection clamps between separate power domains.  It increases the circuit ESD protection by eliminating a diode in the serial ESD chain of components.

Prior methods used cross-coupled diodes for ESD protection between separate power domains.


5,926,064  Floating MOS capacitor

By Dan Hariton -- Filed 1998



This invention allows the formation of a floating capacitor with two MOS devices with the additional benefit of a higher breakdown voltage between the capacitor terminals.

Note that a single MOS device creates a capacitor that is tied to the substrate or to the well.


This invention was referenced in Chapter 33 of Jacob Baker's CMOS Mixed-Signal Circuit Design.


5,920,232  Compensated, bias-dependent signal filter and amplifier circuit  

By Dan Hariton -- Filed 1998




This invention utilizes biased MOS transistors as capacitors  and removes the effect of the bias by creating an equivalent DC signal that is subtracted from the output.  It achieves a large AC output signal utilizing ratios of smaller sized and less expensive components.

4,845,466  System for high speed digital transmission in repetitive noise environment

By Dan Hariton et al. -- Filed 1987

This invention allows high-speed communication over a channel that has repetitive noise (such as a power line) by timing repetitive noise occurrence and transmitting high-speed data during quiet intervals with reference to phase zero crossing.

In the the figure to the left, the quiet intervals are represented by the zero levels on the "impulse detect" trace.
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