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Bhumika Narang
B. E., M. Tech

Assistant Professor
Telecommunication Department
CMR Institute of Technology
E-mail ID - bhumika.ng@cmrit.ac.in

Experience
5 Years of Teaching Experience

Area of Interest in Teaching
VLSI Design, SOC Design, Low Power VLSI Design, Logic Design, Hardware Description Languages

Area of Interest in Research
Digital Low Power VLSI Design

 Publications

 

1.     Bhumika Patpatia, Neha Arora, Prof. B. P. Singh, Kavita Mehta, Neelam Swami, An Adiabatic Single Phase N-type and P- type CPAL Technique for Full Adder Design” in Proceedings of International Conference on Emerging Trends in Networks and Computer Communications ETNCC-2011 (22-24 April, 2011) in Udaipur.

 

2.     Bhumika Patpatia, Neha Arora, Prof. B. P. Singh, Kavita Mehta, Neelam Swami, Implementation of Low Power and High Performance Adiabatic D Flip Flop in Inrenational Conference on Electronics, Information and Communication System Engineering (28-30 March, 2011) in Jodhpur.

 

3.     Bhumika Patpatia, Neha Arora, Prof. B. P. Singh, Low Power and High Performance Adiabatic D Flip

      Flop in Proceedings of International Conference on Innovative Science & Engineering Technology 

        (8-9 April, 2011) in Rajkot.

 

4.     Bhumika Patpatia, Neha Arora, Prof. B. P. Singh, Synthesis of Low Power High Performance

      Adiabatic D Flip Flop, in Proceedings of International Conference on Recent Advances and Trends 

        on Electronics (4-6 March, 2011) at Tamilnadu.

 

5.     Bhumika Patpatia, Neha Arora, Prof. B. P. Singh, Kavita Mehta, Neelam Swami, Implementation of Low Power 2-Phase CPAL D and JK Flip Flop”, in Proceedings of Second National Conference on Recent Advances in Electronics & Communication Technologies (4-5 March, 2011) at Ludhiana.

 

6.     Bhumika Patpatia, Neha Arora, Prof. B. P. Singh, Kavita Mehta, Neelam Swami, Comparative     

     Analysis of Low Power Adiabatic D and JK Flip Flop in Proceedings of National Conference on   

     Knowledge Intelligence and Telemetics (11-12 March, 2011) at Mehsana.

 

7.     Kavita Mehta, Neha Arora, Prof. B. P. Singh, Neelam Swami, Bhumika Patpatia, Implemantation of Low Power High Performance  D  Flip  Flop  Design,  in  Proceedings  of  International  Conference  on  Recent  Advances  and  Trends  on Electronics at (4-6 March, 2011) Tamilnadu.

 

8.     Kavita Mehta, Neha Arora, Prof. B. P. Singh, Neelam Swami, Bhumika Patpatia Comparative Analysis of Low Power Latch Design in  Proceedings  of  National  Conference  on  Knowledge  Intelligence  and  Telemetics  (11-12  March,  2011)  at Mehsana.

 

9.     Neelam Swami, Neha Arora, Prof. B. P. Singh, Kavita Mehta, Bhumika Patpatia, Low Power High Speed CMOS Circuit Design in Proceedings of International Conference on Emerging Trends in Networks and Computer Communications ETNCC-2011 (22-24 April, 2011) in Udaipur.

 

10.  Neelam Swami, Neha Arora, Prof. B. P. Singh, Kavita Mehta, Bhumika Patpatia, Synthesis of High

       Performance Low Power CMOS Circuit Design in Proceedings of International Conference on  

      Recent Advances and Trends on Electronics at (4 -6 March, 2011) Tamilnadu.

 

11.  Neelam Swami, Neha Arora, Prof. B. P. Singh, Kavita Mehta, Bhumika Patpatia, Ultra Low Power

       CMOS Circuit Design in Proceedings of National Conference on Knowledge Intelligence and

       Telemetics (11-12 March, 2011) at Mehsana.

 

12.  Kavita Mehta, Neha Arora, Prof. B. P. Singh, Neelam Swami, Bhumika Patpatia, Low Power High Performance D Flip Flop Design”, in Proceedings of Second National Conference on Recent Advances in Electronics & Communication Technologies (4-5 March, 2011) at Ludhiana.

 

13.  Kavita Mehta, Neha Arora, Prof. B. P. Singh, Neelam Swami, Bhumika Patpatia, “Energy Efficient Low Power D Flip Flop in Proceedings of International Conference on Emerging Trends in Networks and Computer Communications ETNCC -2011 (22-24 April, 2011) in Udaipur.

 

14.  Bhumika Patpatia, Low Power High Speed Adiabatic Full Adder, in Proceedings of National

     Conference on Advances on Recent Technologies in Communication & Computing (10-11 September,

       2011) at Bikaner.

 

15. Bhumika Narang, “Layout Design and Implementation of Adiabatic based Low Power CPAL Ripple 

       Carry Adder” in International Journal on Recent and Innovation trends in Computing and  

       Communication in Vol. 1, Issue 5, Page no. 453-457.


Subpages (1): Logic Design Lab