Amit Jain
        B.Tech, M.Tech, PhD
        Associate Professor, Department of ECE
        E-mail ID: amit.j@cmrit.ac.in
          
 




Areas of Interest in Teaching

Basic Electronics
Analog Electronics
Digital Electronics
Analog VLSI
Digital VLSI,
RF-VLSI

Areas of Interest in Research

Analog and Mixed mode VLSI Cicruits
Analytical Modelling of Nanodevices
Design and Simulation of Single Electronics and SET-MOS Hybrid Circuits
Reliability and Stability analysis of Single Electronics Circuits

Journal Publications

  • "Nanoelectronic Data Transfer System with an Emphasis on Reliability and Stability Analysis", Analog Integrated Circuits and Signal Processing, Springer, 2019 
  • “Error Probability Independent Delay Analysis of Single Electronics Circuits”, International Journal of Circuit Theory and Applications, Wiley DOI: 10.1002/cta.2389, 2018.
  • “Small Signal Model for The Single Electron Transistor: Part I” Journal of Computational Electronics, Springer, 2017.
  • “A Nanoelectronic Neuron Cell for Image Processing Application Based on CNN Architecture”, Journal of Nanoelectronics and Optoelectronics, American Scientific Publishers, 11, 356-362, 2016.
  • “A modified macro model approach 
  • for SPICE based simulation of single electron transistor”, Journal of Computational Electronics, 
  • Springer, DOI 10.1007/s10825-015-0790-1, 2016. 
  • “A new compact analytical model of single electron transistor for hybrid SET–MOS circuits” Solid-State Electronics, Elsevier, 104, 90-95, 2015.
  • “A new SPICE macro model of single electron transistor for efficient simulation of single-electronics circuits”,  Analog Integrated and Signal Processing, Springer 82, 653-662, 2015.
  • “Implementation Aspects of Logic Functions using Programmable Logic Array Architecture with Single Electron Devices and SET-MOS Hybrid Approach”, IETE Journal of Research, 2015.
  • “Analytical modeling of read noise margin of a CNFET based 6T SRAM cell”, Analog Integrated Circuits and Signal Processing, Springer, 83, 369-376, 2015.
  • “Stability and Reliability Analysis of Hybrid CMOS-SET Circuits—A New Approach”, Journal of Computational and Theoritical Nanoscience, American Scientific Publishers, 11(12) 2519-2525, 2014. 
  • “Reliability Aspects and Performance Analysis of Single Electron Threshold Logic Based Programmable Logic Array”, Accepted for Publication in Journal of Computational and Theoritical Nanoscience, American Scientific Publishers, 12 2405-2414, 2014. (I.F.—1.7)
  • “On Simulation of Single Electron Transistor”, Asian Journal of Chemistry, 25, S409-S410, 2013.
  • “Design and Reliability Analysis of a 4:1 Mux Using Single Electron Tunneling Technology Based Threshold Logic Gate” Journal of Electron Devices, 15, 1241-1248, 2012.

International Conference Publications

  • "A 0.5 V LNA Design for 2.4 GHz Wireless Body Area Network Applications" ICECA, 2019
  • "Millimeter-Wave Analog Pre-distorted Power Amplifier at 65nm Node " ICCSPA, 2019
  • “Single electron threshold logic based Feynman gate implementation”, IEEE ICRICN, 2016
  • “Design and implementation of an 
  • asynchronous arbiter circuit using SET-CMOS hybrid architecture approach”, International Conference on 
  • Computing, Communication & Automation 
  • “Stability aspects of single electron threshold logic based 4 bit carry look ahead adder”, C3IT, Academy of Technology, West Bengal, 2015.
  • “Single Electron Threshold Logic Based Neuron Cell for Image Processing Application Based on CNN Architecture”, NANOCON, Pune, 2014.
  • ”Design and Implementation of SET-CMOS hybrid half subtractor”,INDICON 2014, Pune.
  • “Single Electron Threshold Logic Based Neuron Cell for Image Processing Application Based on CNN Architecture”, NANOCON, Pune, 2014.
  • “Low power binary multiplier using SET-CMOS hybrid” NANOCON, 2014, Pune.
  • “Design and Simulation of Hybrid SET-MOS Pass Transistor Logic Based Universal Logic Gates” in IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology (ICECCN), Tamilnadu, 2013.
  • “On Reliability and Stability Analysis of Single Electronics Circuits” Proc. of International Conference on Emerging Technologies - Micro to Nano (ETMN), Goa, 2013.
  • ”Design and Simulation of Single Electron Threshold Logic Gate based Programmable Logic Array” , In 1st International Conference on Computational Intelligence: Modelling, Techniques and Applications (CIMTA- 2013).
  • “Implementation of Programmable Logic Array using SET-CMOS Hybrid Approach” In IEEE conference ICECCN 2013, Tamilnadu 2013. 
  • “Comparative study and analysis of 32 nm FD SOI/SON and CNFET based 4X4 SRAM cell array”, ICCPCT, Tamilnadu, 2013.
Book Chapter


  •   “A Comparative Study of Single electron threshold logic based and SET-MOS hybrid based half subtractor”, Computational   Advancement in Communication Circuits and Systems, vol. 335, Springer, series lecture notes in electrical engineering, pp. 367-373.

Conference Presentations

  • Presented the paper entitled “, “Single Electron Threshold Logic Based Neuron Cell for Image Processing Application Based on CNN Architecture” in NANOCON, Pune, 2014.
  • Presented the paper entitled “Design and Simulation of Hybrid SET-MOS Pass Transistor Logic Based Universal Logic Gates” in IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology (ICECCN), Tamilnadu, 2013.



Events Attended
  • New Model Curriculum Workshop for PG course organized by VTU, Belagavi, 2019
  • VLSI Analog Filters and Sigma Delta Modulators organized by VTU, Belagavi, 2019
  • CMOS and Beyond CMOS Circuits and System Design” by Special Manpower Development Project (SMDP) Lab, Jadavpur University & IEEE EDS Chapter (Kolkata Section) in association with Synopsys Inc., Jadavpur University, Kolkata, 2013.