Ryuta Kawano

Amano-Lab, Dept. of Information and Computer Science, Keio University

Keywords: Interconnection Networks, Deadlock-free Routing, High Performance Computing, Low-latency Network Topology, Network-on-Chips

Biography

  • In Dec 1989, he was born in Hiroshima, Japan.
  • In Mar 2013, he received the B.E. degree from Keio University, Japan.
  • From Oct 2013 to Feb 2015, he was a research assistant in Koibuchi Lab., National Institute of Informatics.
  • In Mar 2015, he received the M.E. degree from Keio University, Japan.
  • From Apr 2015 to Mar 2018, he was a JSPS Research Fellow (DC1).
  • In Mar 2018, he received the Ph.D. degree from Keio University, Japan.
  • From Apr 2018 to Mar 2019, he was a post-doc researcher in Amano Lab., Keio University, Japan.
  • From Apr 2019 to present, he is an assistant professor (non-tenure) in Amano Lab., Keio University, Japan.

Journal (International)

    1. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Generalized Theory based on the Turn Model for Deadlock-Free Irregular Networks", IEICE Transactions on Information and Systems (to be published).
    2. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Layout-Oriented Routing Method for Low-Latency HPC Networks", IEICE Transactions on Information and Systems, Vol.E100-D, No.12, pp.2796–2807, Dec 2017.
    3. Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano, "Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator", IEICE Transactions on Information and Systems, Vol.E100-D, No.12, pp.2828–2836, Dec 2017.
    4. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing", IEICE Transactions on Information and Systems, Vol.E100-D, No.8, pp.1798–1806, Aug 2017.

International conference

    1. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, "k-Optimized Path Routing for High-Throughput Data Center Networks", Proc. of the 6th International Symposium on Computing and Networking (CANDAR'18), pp.99–105, Nov 2018. [Paper] (Outstanding Paper Award)
    2. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "HiRy: An Advanced Theory on Design of Deadlock-free Adaptive Routing for Arbitrary Topologies", Proc. of the IEEE 23rd International Conference on Parallel and Distributed Systems (ICPADS'17), pp.664–673, Dec 2017. [Paper] [Slide]
    3. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "LOREN: A Scalable Routing Method for Layout-conscious Random Topologies", Proc. of the 4th International Symposium on Computing and Networking (CANDAR'16), pp.9–18, Nov 2016. [Paper] (Best Paper Award)
    4. Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano, "Body bias grain size exploration for a coarse grained reconfigurable accelerator", Proc. of the 26th International Conference on Field-Programmable Logic and Applications (FPL'16), Poster session, pp.330–333, Aug 2016.
    5. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "ACRO: Assignment of Channels in Reverse Order to Make Arbitrary Routing Deadlock-free", Proc. of the 15th IEEE/ACIS International Conference on Computer and Information Science (ICIS'16), pp.565–570, Jun 2016. [Paper]
    6. Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Optimized Core-links for Low-latency NoCs", Proc. of the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'15), pp.172–176, Mar 2015. [Paper] [Slide]
    7. Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Configurable Switch Mechanism for Random NoCs", The Poster Session at the 17th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII), Poster session, Poster No.15, Apr 2014. (Featured Poster Award)
    8. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "Low Latency Network Topology Using Multiple Links at Each Host", The Poster Session at the 16th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), Poster session, Poster No.18, Apr 2013. [Poster]

Journal (Japanese domestic)

    1. Ryuta Kawano, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, "The Study of Low-latency On-chip Topology using Multiple Core Links", IEICE Transactions on Information and Systems, Vol.J97-D, No.3, pp.601–613, Mar 2014.

Invited talk

    1. Ryuta Kawano, "Scalable routing techniques for the optimized interconnection networks", CANREXI (CANDAR Extreme Infrastrcture), Takayama Cultural Hall, Japan, Nov 2018.

Awards

    1. "Outstanding Paper Award", The 6th International Symposium on Computing and Networking (CANDAR'18). [Photo]
    2. "Best Paper Award", The 4th International Symposium on Computing and Networking (CANDAR'16). [Photo]
    3. "IEICE ICD Young Presentation Award" (2016).
    4. "IEICE CPSY Young Presentation Award" (2013).

Nomination

For co-authors

    1. Seiichi Tade, "Featured Poster Award", The 17th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVII).

Acknowledgment

A part of our work is supported by JST CREST, a Grant-in-Aid for Young Scientists (B) from JSPS KAKENHI, JSPS KAKENHI S Grant Number 25220002, JSPS KAKENHI Grant Number 15J03374, National Institute of Informatics (NII) Publicly Offered Collaborative Research (General Research), and SCOPE R&D to foster young ICT researchers.

Papers

Slides

Posters