Hello! I am a PhD candidate (in my final semester) in Computer Engineering (Computer Systems) program at School of Computing and Augmented Intelligence (SCAI), Arizona State University. Before that, I earned my master's at ASU in Computer Engineering in 2016. I am currently affiliated with Compiler Microarchitecture Lab / Make Programming Simple Lab and Center for Embedded Systems (CES) and Center for Intelligent, Distributed, Embedded Applications and Systems (IDEAS), where I work with Prof. Aviral Shrivastava on "Agile and Sustainable, Accelerated Computing".
More About My Research
Topics: My research techniques and infrastructures enable the efficient processing of critical applications such as machine learning on hardware accelerators in an agile and sustainable manner. More specifically, my research develops compilation and mapping optimizations for hardware accelerators, execution cost modeling and bottleneck characterization of domain-specific architectures, language for automated accelerator designs, efficient dense/sparse tensor computations, accelerator simulators, and exploration of hardware/software co-designs through systematic heuristics and machine learning.
Presenting findings, visibility, brief note on impact: My research is regularly published in and referred by the top ACM/IEEE conferences and journals in these domains (design automation, embedded systems, computer architecture) and has been featured in premier industrial and global forums. Find more about my comprehensive survey on machine learning accelerator systems here; Video somewhat summarizing my previous research at ASU here; Vision paper for "Accelerator Design 2.0" here (Summary Talk). My research and vision has directly contributed to ASU's project acceptance and participation in highly competitive national projects (including Semiconductor Research Corporation's AI Hardware program, NSF/Intel Research Center on Computer Assisted Heterogeneous Programming) and a new topical course at ASU (on Machine Learning Accelerator Design; See Reading List).
Industry experience, honors, and professional activities: My industry experiences include compiler optimizations for wide-scale commodity embedded systems, as well as digital design and verification for FPGA-based accelerators and ASICs. I am also experienced in piloting novel research projects and system infrastructures, both in collaboration with expert industry/academic researchers and internships (Intel Labs, ARM Research, MathWorks Research, Space Application Center–ISRO, etc.). In addition to being featured in various technical and industry forums, my research has received several competitive honors and awards, including doctoral fellowhips and outstanding research awards, e.g., from ASU and ACM conferences. I regularly serve in various professional and community activities, including reviewing papers for top ACM/IEEE conferences and journals and on program or organizing committee for top conferences and workshops (DAC, ESWEEK, ASPLOS, FCCM, ICCAD, RTSS, Sensors, TCAD), leading vision programs/workshop for future research, and various mentorship programs and activities (IEEE Eta Kappa Nu and ACM SIGARCH/IEEE TCCA Computer Architecture Student Association for mentoring beyond ASU).
Research Interests and Prior Experience
Programmable Domain-Specific Architectures (DSAs)
Agile and Sustainable Design Automation
Machine Learning for Systems
Explainable Design Methodologies for Computing Systems
Computer Architecture and Microarchitecture
Compiler Design and Optimizations
Domain-Specific Programming Language (DSL) Design
Hardware/Software Co-Design
High-Performance, Energy-efficient Computing
Deep Learning and DNN Model Compression
Embedded and Cyber-Physical Systems
Execution Modeling and Bottleneck Characterization
Distributed, Wide-Scale, Real-Time Edge Computing
Alongside, I am always interested in hardware/software codesign research in tandem with the needs of emerging technologies/applications (e.g., AI for AI, federated and on-device learning, fully homomorphic encryption, time-sensitive application programming and execution, low-overhead security and reliability) -- and not as afterthought.
Open to New Industry Research Opportunities!
Note: From mid-September 2023, I would be looking/applying for full-time research scientist opportunities for cutting-edge industrial research (tailored towards "Accelerator Design 2.0"). Please reach out to me if your research group leads/innovates in this area. Here is my envisioned research objective where I would like to contribute/innovate:
“Enable Agile, Sustainable, and Learning-Assisted Automated Exploration of Efficient Domain-Specific Architectures and Systems through Research, Development, and Demonstration at Scale” [Brief Position Paper] [Short Talk]
News:
Our work on making processor design space exploration more explainable is covered by ASU's Fulton Schools of Engineering and featured on ASU news front page, ASU alumni news, ASU Ira Fulton Engineering and SCAI front pages, ACM (Association of Computing Machinary) Tech News, Communications of the ACM (CACM) news, industry blogs, local media, etc. [News Article]
My paper titled "Automating the Architectural Execution Modeling and Characterization of Domain-Specific Architectures" is accepted to appear at SRC TECHCON 2023 (session on sustainable processes). [Paper] [Infrastructure - Coming Soon!]
Honored to author a chapter on "Sustainable Computing Architectures" in the advisory report for National Science Foundation (NSF) workshop on Sustainable Computing.
My mentee Hongyu(ETH Zurich)'s paper, titled "EnergAt: Fine-Grained Energy Attribution for Multi-Tenancy" is accepted for publication in Annual ACM Workshop on Sustainable Computer Systems (HotCarbon) 2023.
My paper titled “Explainable-DSE: An Agile and Explainable Exploration of Efficient Hardware/Software Codesigns of Deep Learning Accelerators Using Bottleneck Analysis” is accepted to appear at the ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). Thanks to my co-author Profs. Tony Nowatzki (UCLA) and Aviral Shrivastava (ASU). [Paper] [Slides] [Poster] [Teaser] [News Article] [Infrastructure - Coming Soon]
Looking forward to attending/presenting at annual review meeting of Semiconductor Research Corporation.
Honored to be invited for ASU Celebration of Excellence 2022-2023 (ASU's student fellows and national honorees).
Will present a virtual seminar talk at Intel Labs on "Agile and Explainable AI Hardware/Software Codesign".
Serving again on the program committee for Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), co-located with ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2023. Consider submitting and/or attending!
Our research directions and vision leads to our project proposal acceptance for funding through competitive SRC AI hardware (AIHW) program from Semiconductor Research Corporation (Multiple industrial groups)! We are excited for researching on sustainable and agile AI hardware development through "AI for AI". Thanks SRC and our industry mentors!
Looking forward to participate in NSF Workshop Panel Discussions on Sustainable Computing as a topical expert for “Architectures” track! Consider attending.
We are invited for a special session on "Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level" in the 26th International Conference on Design Automation and Test in Europe (DATE 2023). [Paper]
We have developed and are teaching a new course on "Topics in Machine Learning Accelerator Design" at ASU in Spring 2023. [Reading List]
Honored to receive silver medal at ACM Student Research Competition (SRC), hosted by ACM SIGBED (Special Interest Group on Embedded Systems) at the 18th ACM/IEEE ESWEEK 2022. Thanks ACM!
Will present on agile and explainable exploration of efficient deep learning accelerators at IBM-IEEE CAS/EDS AI Compute Symposia 2022.
Serving as a mentor for annual Computer Architecture Long-term Mentoring (CALM) program.
Will join IEEE HKN GradLab Episode to talk about graduate school experiences (theme for August: Interpersonal lab relationship). If you have any specific questions to discuss, feel free to send me. [Feature Post] [Video]
Will be presenting our survey and takeaways about "Efficient Sparse NN Processing on Hardware Accelerators: Survey and Insights" at Annual Sparsity in Neural Networks 2022 workshop, co-located with ICML 2022. [Poster]
Serving as a social media chair for the second term for ACM/IEEE Embedded Systems Week. You may follow LinkedIn or Twitter pages for getting regular updates. Register here!
Invited to give a talk on "Agile and Explainable Exploration of Efficient Hardware/Software Codesigns of Deep Learning Accelerators" at DAC-ROAD4NN: Annual International Workshop on Research Open Automatic Design for Neural Networks at 59th annual ACM/IEEE/ESDA Design Automation Conference (DAC 2022). [Check previous edition here.]
Looking forward to attend HotCarbon workshop on Sustainable Computer Design (co-located with USENIX OSDI 2022).
My research work is featured in the IEEE Bridge - Graduate Research Spotlight (in volume 118, issue 2). [Social Media Announcement] (See previous issues here.)
Our group will give a demo on "Efficient Hardware/Software Codesigns of NPUs in Minutes!" at ACM SIGDA University Demonstration, DAC 2022. See Teaser.
Honored to be recipient of the merit-based "Graduate College Completion Fellowship" from the Arizona State University (merit based award for ~0.5% of graduate students, subjected to ASU-wide selection process.)
My dissertation research on "Accelerator Design 2.0: Agile, Efficient, Explainable, and Sustainable" appears at PhD forum in DAC 2022 (59th annual ACM/IEEE/ESDA Design Automation Conference) and IPDPS 2022 (36th IEEE International Parallel & Distributed Processing Symposium).
We are invited to organize a special session on "Towards an Agile Design Methodology for Efficient, Secure, and Reliable ML Systems" at the 40th IEEE VLSI Test Symposium (VTS), 2022. [Paper] [Slides]
Honored to receive the competitive "Outstanding Research Award" from ASU Graduate and Professional Students Association for 2021-2022 term (About 10-15 students awarded annually from 27,000+ graduate students and ~4800 doctoral students).
Our position paper on "Design Space Description Language for Efficient Next-Gen Hardware Accelerators" is accepted in annual LATTE workshop, co-located with ASPLOS 2022. [Paper] [Talk]
Serving on the program committee for Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), co-located with ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). Consider submitting and/or attending! (Papers due: January 25, 2022, Event: March 01, 2022)
Invited to participate in Inaugural Google Systems Innovation Summit, 2021 (with global top PhD students in computing!). (organized by Systems infrastructure research @ Google.)
Our comprehensive survey on accelerating sparse and compact ML/DNN models is published in the Proceedings of the IEEE –the flagship IEEE publication. (impact factor: 14.91)
Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights. Shail Dave (ASU), Riyadh Baghdadi (NYU/MIT), Tony Nowatzki (UCLA), Sasikanth Avancha (Intel Parallel Computing Lab), Aviral Shrivastava (ASU), Baoxin Li (ASU). [arXiv, DOI, summary tweet-thread, Poster]