HAEYEON RACHEL KIM
HAEYEON RACHEL KIM
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This is Haeyeon Rachel Kim, a Ph.D candidate in electrical engineering at KAIST, South Korea. I am currently a member of terabyte interconnection and package laboratory (TERA Lab) advised by professor Joungho Kim.
My field of research focuses on machine learning-based hardware design optimization. I mainly work on building neural architectures and learning schemes for simulation-intensive and NP-hard hardware design problems.
Research field
Research field
Power Integrity and Signal Integrity
Power Distribution Network Design of 2.5D/3D ICs
Machine Learning (Reinforcement Learning, Imitation Learning, Offline Learning)
Hardware Design Automation