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AVR Peripherals

Starting with VMLAB version 3.15, it's possible to create external user components that emulate AVR peripherals such as timers, UARTs, etc. The components on this page currently implement only a few of the peripherals found in the ATmega168. My long term goal is to create a user component for every peripheral found in all of the ATmega and ATtiny series of microcontrollers. These components are licensed under the GNU LGPL v2.1.

Usage

To simulate a ATmega168 microcontroller with the new peripheral components, use a .MICRO "ATmega168b" directive in your project file. The "b" at the end of the micro name is necessary to select the new model; without it, the old internal ATmega168 model would be used. Also keep in mind that apart from the peripherals listed here, all other peripherals are still implemented using the old builtin models that don't quite match the real hardware of the 168.

Downloads

When downloading a new version of the AVR peripherals, always make sure to replace every one of the old DLL and INI files in the "mculib" directory with the newer versions contained in the zip file. Because these components closely interact with each other, updating only some of the files could cause unpredictable behavior and even crashes due to the version mismatch.
  • useravr.zip - Contains the precompiled DLL files. Install into the "mculib" directory.
  • useravr-src.zip - Contains the source code to all peripheral components.

Supported Peripherals

This section explains in great detail what AVR peripherals are currently emulated and how accurate that emulation is. Text in blue is used to describe any unusual behavior that may be confusing for someone who is new to VMLAB or AVRs. Text in red describes any differences between the behavior of the emulated peripheral and the real AVR hardware. In general, 1 to 6 clock cycle delays due to synchronization, edge detection circuits, etc. will not be emulated.
  • General I/O Pins
    • PORTx, PINx, DDRx registers are emulated. Pin toggling is supported. Writing a 1 bit to a PINx bit will toggle the corresponding bit in the PORTx register.
    • If another peripheral overrides the direction and/or output value of a pin, then that pin will not automatically return to its previous state (as defined in DDRx and PORTx) when the peripheral function is turned off. The pin state will not change until the DDRx and/or PORTx registers are updated again.
    • The 1.5 clock cycle input delay due to synchronization of the I/O pin is not emulated. After writing PORTx, VMLAB doesn't require a "nop" instruction when immediately reading back the software assigned pin value through PINx. See the "Reading the Pin Value" section in the datasheet for more information.
  • Sleep Mode
    • The SMCR register and the SLEEP instruction are emulated. All sleep modes are supported.
    • Only the TIMER0 and TIMER1 peripherals are currently guaranteed to behave correctly during sleep mode.
  • TIMER0
    • All timer registers are emulated. The TSM & PSRSYNC bits in GTTR and the PRTIM0 bit in PRR is emulated. All waveform generation modes, output compare modes, and timer clock sources are emulated.
    • The OCR0A/B registers are double-buffered in PWM waveform generation modes. Changing either register in the GUI will actually change the value in the buffer first. You may have to right click on the registers and select "Modify / browse" from the pop-up menu to make your changes atomic.
  • TIMER2
    • All timer registers are emulated. The TSM & PSRASY bits in GTTR and the PRTIM2 bit in PRR is emulated. All waveform generation modes, output compare modes, and timer clock sources are emulated.
    • Asynchronous operation with either a 32.768kHz watch crystal or an external clock signal on the TOSC1 pin is emulated. All side-effects described in the "Asynchronous Operation of Timer/Counter2" section in the datasheet are emulated, and VMLAB will issue warnings if any potentially undesirable behavior occurs.
    • The datasheet warns that all timer registers except for ASSR may be corrupted when switching to and from asynchronous mode or when waking up from sleep while in asynchronous mode. VMLAB can optionally emulate this behavior by setting all affected registers to unknown (i.e. XXXXXXXX) if the "Async Corrupt" option in the GUI is checked.
    • In asynchronous mode, updates to all registers except ASSR are delayed by two asynchronous clock cycles. When modifying the registers in the GUI, the new values will not be immediately visible. This is in addition to the OCR2A/B double-buffering done in PWM waveform generation mode. You may have to right click on the registers and select "Modify / browse" from the pop-up menu to make your changes atomic.
    • Asynchronous mode can be enabled while using an external system clock (based on CKSEL fuse settings). On real hardware, asynchronous mode can only be used with the internal RC oscillator system clock because the TOSC and XTAL functions are shared by the same set of pins.
    • Signal changes on the TOSC1/2 pins continue to trigger PCINTx interrupts while the timer is in asynchronous mode.
    • The datasheet advises waiting at least 1 second after enabling asynchronous operation so the oscillator can stabilize. VMLAB does not enforce or emulate this behavior; the timer is immediately available for use after entering asynchronous mode.

Version History

  • v0.2 - 10/09/09 - TIMER2 model released
  • v0.1 - 09/15/09 - TIMER0 model released