The following components implement 8-bit digital data inputs and outputs that use log and stimulus files in the same "NNNNNNNNN:XX" format as the AVR Studio simulator where the Ns are the MCU cycle count in decimal and the XX is the stimulus value in hex. Note that AVR Studio simulates a 1.5 clock cycle debouncing delay on all inputs while VMLAB does not. To get identical cycle counts, the avrstim component manually adds the 1.5 cycle delay to all output changes. Downloads
; To use either component, use one of the following definitions: ; ; X<Name> _avrstim(<ClockFrequency>) <D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0> ; X<Name> _avrlog(<ClockFrequency>) <D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0> ; ; The <Name> is used to form part of the filename in the format "<Name>.sti" for ; the stimulus component and "<Name>.log" for the logging component. The ; <ClockFrequency> is specified in Hz (.e.g. "1MEG") and should match the actual ; MCU clock frequency being simulated to ensure correct cycle counts in the ; input/output files. The <D7-D0> nodes are the digital outputs driven by the ; stimulus file (D7 is the MSb), or the digital inputs written to the log ; file. ExampleXinput _avrstim(1meg) pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0Xoutput _avrlog(1meg) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 Version History
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