I am an R&D Engineer with Freescale Semiconductor's Networking & Multimedia Group, designing PowerPC processor cores used in a variety of embedded products. Prior to this position, I was with the Exploratory VLSI/Tools and Technology group at IBM's Austin Research Lab.

Select Publications
  • R. Kanj, R. Joshi, J. Sivagnaname, JB Kuang, D. Acharyya, T. Nguyen and S. Nassif, “Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs,” IEEE Trans. On Semiconductor Manufacturing, vol. 21, pp. 33-40, Feb. 2008.
  • J. Sivagnaname, H. Ngo, K. Nowka, R. Montoye and R. B. Brown, “Wide Limited Switch Dynamic Logic Circuit Implementations,” VLSI Design Conference, pp. 94-99, Jan. 2006.
  • J. Sivagnaname, H. Ngo, K. Nowka, R. Montoye and R. B. Brown, “Controlled-load Limited Switch Dynamic Logic Circuit,” ISQED, pp. 83-87, Mar. 2005.
  • J. Sivagnaname and R. B. Brown, “Stand-by Current in PD-SOI Pseudo-nMOS Circuits,” IEEE International SOI Conference, pp. 95-96, Sep. 2003.
  • C. Gauthier, J. Sivagnaname and R. B. Brown, “Dynamic Receiver Biasing for Inter-Chip Communication,” 2001 Conference on Advanced Research in VLSI, pp. 101-111, May 2001.
  • T. A. Grotjohn, J. Asmussen, J. Sivagnaname, D. Story, A. L. Vikharev, A. Gorbachev, and A. Kolysko, "Millimeter Wave Fabry-Perot Resonator Plasma Diagnostic Measurements of Electron Density in Moderate Pressure Diamond Deposition Discharges," Diamond and Related Materials, vol. 9, pp. 322-327, 2000.
Patents
  • “Method and Apparatus of Measuring Device Mismatches,” US Patent #7408372, issued Aug. 2008.
  • “Method and Apparatus of Measuring Device Mismatches,” US Patent pending (application no. 2008/0258752 A1), filed Jun. 2008.
  • “An Active Cancellation Matrix for Process Parameter Measurements,” US Patent #7394276, issued Jul. 2008.
  • “Controlled-load Limited Switch Dynamic Logic Circuit,” US Patent #7129754, issued Oct. 2006.
  • “High Performance EDRAM Sense Amplifier,” Invention disclosed to IBM on Aug. 2008.
  • “Techniques for Characterizing Performance of Transistors in Integrated Circuit Devices,” US Patent pending (application no. 2009/0251223 A1), filed on Apr. 2008.
  • “Wordline to Bitline Output Timing Ring Oscillator Circuit for Evaluating Storage Array Performance,” US Patent pending (application no. 2009/0027065 A1), filed on Jul. 2007.
  • “Half Select Compliant 8-T SRAM Cell,” US Patent pending (application no. 2009/0027983 A1), filed on Jul. 2007.
  • “Closed-loop Modeling of Gate Leakage for Fast Simulators,” US Patent pending (application no. 2008/0281570 A1), filed on May 2007.
Related work done at The University of Michigan

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