currently, I am working for Intel on EDA for low power chip design. It is very proud for me to receive all scholarships of "Best 3" in my area: - Intel: most successful business in semiconductor,
- IBM Research: most reputable in academic and research
- Peking Univ. : best microelectronics institute of fastest growing market (China)
5/2008 - 12/2008, Austin, TX Intern of lithography simulation and optimization in TOOLS and Technology Group. - Developed a GPU friendly lithography simulator for 45nm to 22nm technology.
- Invented Inverse Lithography Optimization (ILO) based on continuous mask and partial coherent litho system. The new method speeded up the optimization for 10K+ times as it converted N^3 to Nlog(N) complexity.
- Working on lithography simulation and layout analysis of 32nm SRAM and related circuit based on double pattern mask.
- Green method for lithographic process variation modeling and simulation. Speed up the total runtime of lithographic simulation at variation sampling points by 5-20X.
- Dose/defocus process windows tolerant ILO. Greatly reduce the computation overhead of process variations.
Blaze-DFM5/2007 - 8/2007, Sunnyvale, CA Summer intern of parameter extraction of BSIM4 device model in R&D group. - By using Levenberg-Marquet Algorithm and multi-dimensional SPLINE to extract model parameter and narrow down the process variations according to Process Control Monitoring (PCM) data.
- Gate and source-drain leakage modeling with post-silicon data analysis.
5/2006 - 9/2006, Yorktown, NY Summer intern of layout analysis and optimization in Design Automation Dept. - Implemented the post-litho device modeling card
- Circuit simulation of latch with the consideration of lithographic variations..
3/2001 - 4/2001, Beijing, China Part-time Programmer,
- Implemented some algorithm of face image recognition in C++.
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