- PhD., Computer Engineering (ECE), The University of Texas at Austin, 2009, expected
- M.S.E., Computer Engineering (ECE), The University of Texas at Austin, Dec. 2008
- M.S., Microelectronics, Peking University, China, Aug. 2004
- B.S., Physics, Peking University, China, Aug. 2001
Selected Awards| 2008 - 2009 | IBM Ph.D. Scholarship | | 2004 - 2005 | 42nd DAC Young Student Support Program Award | | 2003 - 2004 | Distinguished Graduation Thesis, M.S. DEGREE WITH HONORS | 2003 - 2004
| Excellent Winner of "Science Academic Top 10" in Peking University 10/10000 (0.1%) | | 2002 - 2003 | Honor of Innovation, Peking University 1st/3000 (0.1%) | | 2002 - 2003 | Yang Fuqing & Wang Yangyuan Academicians Scholarship, Peking University
| | 2001 - 2002 | Intel Scholarship on Information Science and Technology |
Academic Experience01/2005 - Now, Design Automation Group of Computer Engineering Research Center - Latch design and modeling for statistical timing analysis. Proposed an accurate analytical model for latch and finish statistical timing analysis combining both combinational logic and clock distribution network. Published on DATE 2008.
- Modeling and optimization for stressing effect. First proposed the prototype to optimization timing at detail placement step during physical design. This work is also published on DATE 2008.
- Post-litho device characterization and circuit analysis/optimization based on process variations analysis and modeling. It is the first 3-D post-litho compact device model, published on DAC’06 and ICCAD’06.
- Implement Discrete Cosine Transformation of diffusion force and virtual density for global placement. Based on these methods, the total wire length is reduced by 5%, and the simulation is also speeded up.
- Developed models for wire optimization (sizing/shaping) of interconnection considering scattering effect for nanoscale interconnect. The work was published on ASPDAC'06.
9/2001 - 8/2004, Institute of Microelectronic in EECS Dept. - Research Assistant of PKU & SMIC cooperative project
Developed new process variation models for short channel devices, and invented precise 2-D simulation methods for 50nm and below CMOS devices to replace slow 3-D simulation. The method is also used to analyze the impact of dopant variations with both density and location. Designed testing layout for process variations of 90nm IC manufacturing. Published on Solid-State Electronics and IWJT. - Research Assistant of PKU & Fujitsu cooperative project
Member of TCAD research cooperative project between Peking University (PKU) and Fujitsu Laboratories LTD. Developed process simulation software for semiconductor manufacture of doping and annealing process. Invented a series of new statistical algorithms for molecular dynamics (MD)/Monte Carlo (MC) simulation of ion implantation, and speeded up the simulation by up to more than 50 times. Published on IWJT, MRS, etc.
CoursesVLSI-1
| VLSI-2
| Optimization Issues in VLSI CAD | VLSI Physical Design Automation | Nanometer Scale IC Design
| Engineering Programming Language
| Dependable Computing
| Computational Microelectronics
| Analysis and Design of VLSI Circuits
| Low Power Design for CMOS IC
| New Technology of VLSI
| Digital System Integration
| Nanometer Semiconductor Device
| Physics of Semiconductor Devices
| Analog VLSI
| Introduction to Microelectronic Machine System
| Statistical Methods in Engineering and Quality Assurance
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Teaching Assistant
- EE360 Digital Circuit Design
- Introduction of Microelectronics
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