The objective of this project is to develop an innovative network-on-chip oriented design platform constituting a toolkit for the construction of NoC-based multi-core systems in nanoscale technologies.

The design platform will provide a structured approach to a NoC-based design flow by relying on a vertically integrated interconnect design and optimization strategy, enabling interoperability between tools at different layers of the design hierarchy. It will target efficient complexity management through a strict component orientation, a high degree of flexibility and (re-)configurability, support for high-level virtualization, power and variability management frameworks, integration and reuse of heterogeneous IP cores and verification of the resulting functionality, robustness to manufacturing defects and process variations and fast physical convergence by silicon-awareness throughout the design flow.