Labs

Software

We will be using a software package called Xilinx ISE WebPack 12.4  for digital logic programming in this class. This is free software that can be downloaded from the Xilinx web page. For simulations, we will use the Modelsim software, which is also a free download from the Xilinx web page. We will discuss how to install and use the software in lab. The labs will be oriented around your laptops, so you will need to install the software yourself. You should have the software downloaded before coming to lab since it is a very large download (~1.7).

1. Xilinx ISE WebPack Download - Please be sure to download version 12.4. You will need to register first then return to the above link to download the correct version.
2. Download Adept 2.8.1 - This is used to download .bit files to your Basys board.
   

Hardware

The labs this semester will require each student to purchase the Digilent, Inc. Basys 2 development board. These cost $49 (student version) each and can be purchased directly from the Digilent, Inc. homepage.  Included with each kit is a power supply and download cable. We decided to do this so each student can have hands-on experience with FPGA hardware. Each board has 8 LEDs, 8 switches, 4 push buttons, and a 4 digit numerical display. There are also connections for a VGA monitor and a PS/2 port for keyboards/mice. We will be using all of these in the lab.

1. Basys reference manual
2. Basys board schematic

Lab Tips

• There are 2 Basys boards! The original Basys and the Basys 2. The package and pinout is different between the two boards.

• Board Version	FPGA	Package	Speed Grade	UCF File
  Basys	XC3S100E	TQ144	-4	ucf file
  Basys 2	XC3S100E	CP132	-4	ucf file

   
  
• Make sure you are using the correct package and UCF file for your board.
  
• General:
  • Be sure to include the constraints file in your project. If you're seeing strange things on the outputs, this may be the problem.
  • If your code compiles, but doesn't do what you want it to: READ THE WARNINGS
    • The warnings are there to tell you that you probably made a mistake, but it will compile your code anyway
    • If it optimized something out, it will give you a warning - that's usually a mistake
    • It will tell you when it finds an asynchronous loop
    • It will tell you of unassigned I/O
• Verilog code:
  • Make simple always blocks
    • Only assign few related outputs
    • More smaller process statements are better than one big one
    • The compiler is not very smart
  • Always be able to draw a block diagram of the circuit you are trying to describe
  • Watch out for asynchronous loops in your code
    • Make sure you can't trace a combinatorial path
    • Temporary signals make this deceptive
• Schematic Entry:
  • Use the wire naming tool - don't double click on a wire to name it
  • If you rename a wire, it will rename all of the wires of the same name

Reference Material

• Verilog
  • Verilog HDL Quick Reference Guide
  • Introduction to Verilog
  • Verilog.org
  • An Introduction to the Concepts of Timing and Delays in Verilog
• Other Universities using FPGAs
  • Oregon Institute of Technology
  • University of California, Santa Cruz
  • Worcester Polytechnic Institute
  • LaFayette College

Academic support

In compliance with and in the spirit of the Americans with Disabilities Act (ADA), academic accommodations are made for any student with a documented disability. Students should register with the Office of Student Support Services in Montgomery Hall at (662) 325-3335 as soon as possible to better ensure such accommodations are implemented in a timely fashion and comply with their policies. Any student who believes they may need accommodations in this class are encouraged to contact Student Support Services If Student Support Services has a prescribed course of action for you with regard to this class, please visit me during office hours so we can make the proper arrangements.

Academic Integrity

Mississippi State University has an approved Honor Code that applies to all students. The code is as follows:

"As a Mississippi State University student I will conduct myself with honor and integrity at all times. I will not lie, cheat, or steal, nor will I accept the actions of those who do."

Upon accepting admission to Mississippi State University, a student immediately assumes a commitment to uphold the Honor Code, to accept responsibility for learning, and to follow the philosophy and rules of the Honor Code. Students will be required to state their commitment on examinations, research papers, and other academic work. Ignorance of the rules does not exclude any member of the MSU community from the requirements or the processes of the Honor Code. For additional information please visit the MSU honor code website.

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