System IC (Switch + CPU Processor)

---

• Introduction Images

• Research Goal

• Development of a SPARC processor supplying 1Gbps and 10Gbps interfaces as a government project  
• Development of a switch system using SPARC processor as a government project
  
  

• Research Statistics

• Research resource: 2 people
• Research term: 2006.11 ~ Current (12 months)
• My role responsible of this research: 70%
• Research output: Schematics (Used PADS-Designer), Artwork (Used Mentor), CPLD Module system (Used HDSL Code)
  
  

• Techniques used for this research

• RGMII: Reduced Gigabit Media Independent Interface (RGMII) specifies a particular interface between an Ethernet MAC and PHY. RGMII uses half the number of pins as used in the GMII interface. This reduction is achieved by clocking data on both the rising and falling edges of the clock, and by eliminating non-essential signals (carrier-sense and collision-indication). Thus RGMII consists only of: RXC, RD[3:0], RX_CTL, TXC, TXD[3:0], and TX_CTL (12 pins, as opposed to GMII's 24). RGMII supports Ethernet speeds of 10 Mb/s, 100 Mb/s and 1000 Mb/s.
• XGMII: 10 Gigabit Media Independent Interface (XGMII) is a standard for connecting full duplex 10 Gigabit Ethernet (10GbE) ports to each other and to other electronic devices on a printed circuit board. It is composed from two 32-bits datapaths (Rx & Tx) and two 4-bits control flows (Rxc & Txc), operating at 156.25 MHz.
  
  

• My contribution to the research

• System Archetecture: I design the all system archetecture using SPARC processor which is developed by other company. It's so hard to design this functions on one board because the product has 24 ports which is operated on 1Gbps and 2 ports which is operated on 10Gbps. I could make it stable systme by the methods that I used XPAX module and Marvell 88X2040 to supply 10G interface.
• System Initialization: This platform consist of CPU, Memory(Flash, RAM), PCI-device, 10/100/1000 tranciever and 10G transiver. As we needed to initialize whenever we wanted, I designed the initialization system used CPLD device which contolls all parts for initialization.
• Protolcols: Our system has used 1000/100/10 bps and 10G ethernet interface. Because they are the most important in our system, we should consider and confirm about the protocols to produce the constant output. I modified the signals which are important by parallel and serial termination.
  
  

• Results

Figure1: Artwork result based on System IC (CPU+Swich)


Figure2: Total Artwork result