BCM 1125H MIPS Processor

• Introduction Images

• Research Goal

• Development of a system which supplies sixteen 1Gbps interface by using BCM 1125 MIPS CPU
• Development of a efficient Layer 4 and Layer 7 Load Balancer
  
  

• Research Statistics

• Research resource: 4 people
• Research term: 2006.7 ~ 2006.12 (6 months)
• My role responsible of this research: 20%
• Research output: CPLD Module system (Used HDSL Code) & Schematics (Used PADS-Designer)
  
  

• Techniques used for this research

• BCM1125H: An intelligent system on a chip consisting of a Broadcom SB-1 high performance MIPS64 CPU, a shared 256-KB L2 cache, a DDR memory controller, and an integrated I/O. Two Gigabit Ethernet Macs enable easy interfacing to LANs. High-speed I/O is provided using Hyper''Transport (HT) I/O fabric and a 32-bit PCI local bus.
• SB-1 CPU Core: A high-performance implementation of the standard MIPS64 ISA that incorporates the MIPS-3D and MIPS-MDMX application specific extensions (ASEs). The core supports a 4-issue enhanced skew pipeline and can dispatch up to two memory and two ALU (integer, floating point, MDMX, or MIPS-3D) instructions per cycle.
• BCM1125H Fact Tables

• Hyper Transport Technology (HT): A high-speed, low latency, point-to-point link designed to increase the communication speed between integrated circuits in computers, servers, embedded systems, and networking and telecommunications equipment. We use HT to put access to our SSL Accelerator card through PCI-X.
• SPI-4: SPI-4 is a version of the System Packet Interface published by the Optical Internetworking Forum. It was designed to be used in systems that support OC-192 SONET interfaces and is sometimes used in 10 Gigabit Ethernet based systems.
• Gigabit Media Independent Interface (GMII): It is an interface between the Media Access Control (MAC) device and the physical layer (PHY). The interface defines speeds up to 1000 Mbit/s, implemented using an eight bit data interface clocked at 125 MHz, and is backwards compatible with the Media Independent Interface (MII) specification. It can also operate on fall-back speeds of 10/100 Mbit/s as per the MII specification.
  
  

• My contribution to the research

• System Control: Our switching system usually uses a serial signal to control each devices, such as MDC/MDIO. Although IC devices provide the communication system, I strengthened the parts by using CPLD module.
• System Initialization: Our platform consist of CPU, Memory(Flash, RAM), PCI-device, Watchdog-device, and 10/100/1000 Tranciever. As we needed to initialize whenever we wanted, I designed the initialization system using CPLD device which contolls all parts for initialization. 
• Protolcols: Our system has used 1000/100/10 bps ethernet interfaces. Because they are the most important parts in our system, we should consider and confirm about the protocols to produce the stable output. I modified significant signals by parallel and serial termination.
  
  

• Results

Figure1: Artwork result based on BCM1125H


Figure2: Schematic result based on BCM1125H