My work interests include algorithms and computation with a concentration on programmable logic and FPGAs:   FPGA architecture and the design of interconnection networks, optimization algorithms on graphs for VLSI CAD targeting FPGAs, and applications of FPGAs in communications, DSP and reconfigurable computing.

Aside from FPGAs, I'm interested in graph and optimization algorithms, data analysis, data mining and statistics.  

I am currently a Principal Design Engineer in the Office of the CTO at Altera.  Prior to that I was the Director of Chip Architecture at Tabula.  From 1997-2009 I worked on FPGA architecture and algorithm R&D at Altera, where I participated in the design of most of Altera's FPGA architectures including Apex I/II, Stratix I/II/III/IV/V, Mercury, Cyclone I/II/III, Arria and MAX II families. I also coordinated Altera's external research and funding with Universities.  On the CAD side I have worked on placement (graph embedding), synthesis (boolean logic optimization), and timing analysis (graph traversal and analysis) algorithms.  Most of this is available through publications and patents.  

I earned my Ph.D. in Computer Science from the University of Toronto in 1997 and before that my MMath and BMath degrees in Computer Science from the University of Waterloo.   My Ph.D. thesis advised by Jonathan Rose and Derek Corneil involved a graph-theoretic characterization of the properties of digital circuits for use in developing and evaluating heuristic CAD algorithms such as place&route and FPGA architectures.  The circuit characterization (circ) and graph generation (gen) software is available for download.   My Master's thesis with Anna Lubiw was in graph theory / graph drawing.  In my co-op undergrad, I had work-terms at IBM, Bell-Northern Research (now Nortel), and Environment Canada.   

This picture is from the top of the hill in Capri, Italy, in 2007.