Kishore Malani Mtech, IIT Bombay kishore.malani@ieee.org 9322 972 377 URL: http://sites.google.com/site/klmkishore12345/ EDUCATIONAL QUALIFICATIONS Examination University Institute Year CPI or % MTech IIT Bombay IIT Bombay 2009 8/10 (Microelectronics) Graduation Univ. of Mumbai Thadomal Shahani 2004 62.14 % Engineering College Intermediate/+2 Maharashtra Smt. C.H.M. College 2000 81.67 % State Board Matriculation Maharashtra S.P.P. New Era 1998 82.80 % State Board High School COURSES UNDERTAKEN Hardware Description Languages, VLSI Design, System Design, VLSI Technology TECHNICAL SKILLS • TCAD tools : Sentaurus (SDevice, Structure Editor, Tecplot SV, Inspect) • Hardware Description Language : VHDL • Programming language : C • EDA Tools : ModelSim, Xilinx • Circuit Simulators : Cadence, Eldo, SPICE • Layout tool : MAGIC • Operating system : Linux M.Tech. Thesis (January 2008 - till date) Evaluating Different Logic Styles for Digital Circuits Using 45 nm Devices Principle advisor: Prof. V. Ramgopal Rao • Scaling of devices has resulted in increased static, and hence total power dissipation for CMOS logic. This project is aimed at exploring different technologies and logic styles, to find out the optimum for 45 nm node and below • Modeled MOSFET devices using Sentaurus Structure Editor (SDE) and SDevice, with performance parameters matching Intel’s 45 nm devices • Performed circuit simulations in Cadence to compare different logic styles. Capacitance estimation was based on (a) circuit layouts prepared in MAGIC, (b) ITRS 2007 Update COMPLETED PROJECTS (A) Course Projects during MTech (July 2006 – April 2008) • Hardware Description Language: Designed and implemented 4X4 Data Switch in VHDL, with routing of 32-bit data from any input channel to any output channel without collision • System Design: Designed and implemented a generic 32 bit multiplier using control path and data path decomposition in VHDL • VLSI Design Lab: Designed and laid out a 31-stage ring oscillator in MAGIC and simulated the extracted layout in SPICE • Microelectronics Lab: Fabricated and characterized MOS capacitor (B) Digital Capacitance Meter (July – September 2002) B.E. Project (June 2003 - May 2004) Intelligent Surface Dependent Suction Technique for Vacuum Cleaners Using Fuzzy Logic • Proposed a methodology to increase the efficiency of a conventional vacuum cleaner, by controlling its power supply in real time depending on: (i) surface friction, (ii) amount of dirt, and (iii) operator speed. Fuzzy Logic Toolbox in MATLAB was used to simulate the control. AWARDS AND HONORS 1. Awarded Institute Special Mention for organizing and co-ordinating cultural activities at institute and hostel levels 2. Awarded Best Office Bearer for exceptional work as Photography and Fine Arts secretary of Hostel 12 – with the strength of 500 students 3. Secured a position in top SEVEN teams in Open Hardware Design Competition at TECHFEST 2007, IIT Bombay 4. Awarded certificate of excellence for best working model in inter-collegiate Poster-cum-model competition on Applications of Signals-and-Systems 2004, IIT Bombay POSITIONS OF RESPONSIBILITY 1. Overall Co-ordinator, International Workshop on Physics of Semiconductor Devices (IWPSD 2007) – Headed a 2-tier team of over 60 volunteers, International audience of over 400 from 8 countries 2. Core Team Member, Aagomani 2008, Annual technical event of Electrical Engg. Department – Co-ordinated with speakers and Technical & Events team; designed the schedule 3. Hostel Photography and Fine Arts (PFA) Secretary – Organized an Art Exhibition, first time ever by a hostel in IIT Bombay HOBBIES Nature photography (http://www.flickr.com/photos/klm_kishore/), Dancing, Lawn Tennis, Table Tennis, Yoga EXTRACURRICULAR ACTIVITIES • Represented department in chess, cycling and tri-athlon at PG sports 2007 • Mumbai Marathon 2009: 21 kms.; IIT Bombay Marathon 2008 for 11 kms. STRENGTHS Team player as well as individual performer, listener, organized |