Books / Book Chapters

 

(1)    C. S. Tan, R. Gutmann, and R. Reif (Editors), “Wafer Level 3-D ICs Process Technology,” Springer, ISBN 978-0-387-76532-7, 2008. (Contributed two chapters)

       

 

 

 

 

 

 

 

 

Interested readers can purchase this book from Springer or Amazon.

 (2)   C. S. Tan, A. Fan, and R. Reif (Authors), “Via-First 3-D ICs Fabrication Achieved by Wafer Bonding.” In: Handbook of 3D Integrations – Technology and Applications of 3D Integrated Circuits, P. Garrou, C. Bower, and P. Ramm (Editors), Wiley-VCH, ISBN 978-3-527-32034-9, 2008.

     

Journals

 

(1)      C. S. Tan, W. K. Choi, L. K. Bera, K. L. Pey, D. A. Antoniadis, E. A. Fitzgerald, M. T. Currie, and C. K. Maiti “N₂O Rapid Thermal Oxidation of Strained-Si/Relaxed-SiGe Heterostructure grown by UHVCVD,” Solid State Electronics, 45, pp 1945-1949, 2001.

(2)      L. K. Bera, W. K. Choi, C. S. Tan, S. K. Samanta, and C. K. Maiti, "High Quality Gate Dielectrics Grown by Rapid Thermal Processing Using Split-N₂O Technique on Strained-Si_0.91Ge_0.09 Films," IEEE Electron Device Letter, Vol 22, No 8, pp 387-389, August 2001.

(3)      K. N. Chen, A. Fan, C. S. Tan, R. Reif, and C. Y. Wen, “Microstructure evolution and abnormal grain growth during copper wafer bonding,” Applied Physics Letters, Vol 81, No 20, pp 3774-3776, 2002.

(4)      C. S. Tan, A. Fan, K. N. Chen, and R. Reif, “Low-temperature thermal oxide to Plasma-Enhanced Chemical Vapor Deposition oxide wafer bonding for thin-film transfer application,” Applied Physics Letters, Vol 82, No 16, pp 2649-2651, 2003.

(5)      K. N. Chen, A. Fan, C. S. Tan, and R. Reif, “Temperature and Duration Effect on Microstructure Evolution During Copper Wafer Bonding,” Journal of Electronic Materials, 32(12), pp 1371-1374, 2003.

(6)      K. N. Chen, C. S. Tan, A. Fan, and R. Reif, “Morphology and Bond Strength of Copper Wafer Bonding,” Electrochemical and Solid-State Letters, 7(1), pp G14-G16, 2004.

(7)      K. N. Chen, A. Fan, C. S. Tan, and R. Reif, “Contact Resistance Measurement of Bonded Copper Interconnects for Three-Dimensional Integration Technology,” IEEE Electron Devices Letters, 25(1), pp 10-12, 2004.

(8)      C. S. Tan, K. N. Chen, A. Fan, and R. Reif, “Low temperature direct chemical-vapor-deposition (CVD) oxides to thermal oxide wafer bonding in silicon layer transfer,” Electrochemical and Solid-State Letters, 8(1), pp G1-G4, 2005.

(9)      K. N. Chen, C. S. Tan, A. Fan, and R. Reif, “Abnormal Contact Resistance Reduction of Bonded Copper Interconnects in Three-Dimensional Integration during Current Stressing,” Applied Physics Letters, 86, pp 011903, Jan 2005.

(10)  C. S. Tan and R. Reif, “Multi-layer Silicon Layer Stacking Based on Copper Wafer Bonding,” Electrochemical and Solid-State Letters, 8(6), pp G147-G149, 2005.

(11)   K. N. Chen, S. M. Chang, A. Fan, C. S. Tan, L. C. Shen, and R. Reif, “Process development and bonding quality investigations of silicon layer stacking based on copper wafer bonding,” Applied Physics Letters, 87, pp 031909, July 2005.

(12)  K. N. Chen, C. S. Tan, A. Fan, and R. Reif, “Copper bonded layer analysis and effects of copper surface conditions on bonding quality for three-dimensional integration,” Journal of Electronic Materials, 34(12), pp 1464-1467, 2005.

(13)  C. S. Tan and R. Reif, “Microelectronics Thin Films Handling and Transfer using Low Temperature Wafer Bonding,” Electrochemical and Solid-State Letters, 8(12), pp G362-366, 2005.

(14)  C. S. Tan, K. N. Chen, A. Fan and R. Reif, “The effect of forming gas anneal on the oxygen content in bonded Cu layer,” Journal of Electronic Materials, 34(12), pp 1598-1602, 2005.

(15)   C. S. Tan, R. Reif, D. Theodore, and < xml="true" ns="urn:schemas-microsoft-com:office:smarttags" prefix="st1" namespace="">S. Pozder, “Observation of Interfacial Voids Formation in Bonded Copper Layer,” Applied Physics Letters, 87(20), pp 201909, 2005.

(16)  K. N. Chen, A. Fan, C. S. Tan, and R. Reif, “Bonding parameters of blanket copper wafer bonding,” Journal of Electronics Materials, 35(2), pp 230-234, 2006.

 

Conferences (Presenter is underlined)

 

(1)    C. S. Tan, W. K. Choi, K. L. Pey, and L. K. Bera, “Electrical Characterisation of Rapid Thermal Oxides grown on strained Si/relaxed SiGe Heterostructure,” Proceeding of the  Electrical Engineering Conference 2000, University of Malaya, Malaysia, August 8-9, 2000.

(2)   C. S. Tan, W. K. Choi, L. K. Bera, K. L. Pey, D. A. Antoniadis, E. A. Fitzgerald, M. T. Currie, and C. K. Maiti “N₂O Rapid Thermal Oxidation of Strained Si/Relaxed SiGe Heterostructure grown by UHVCVD,” Proceeding of the International Conference on Computer, Communication and Devices, IIT Kharagpur, India, December 14-16, 2000.

(3)   C. S. Tan, W. K. Choi, K. L. Pey, L. K. Bera, D. A. Antoniadis, E. A. Fitzgerald, and C. W. Leitz, “Rapid Thermal Oxidation of Strained Si/Relaxed SiGe Heterostructure,” Proceeding of the Singapore-MIT Alliance Annual Symposium, National University of Singapore, January 16-17, 2001.

(4)   E. A. Fitzgerald, M. T. Currie, C. W. Leitz, M. Armstrong, G. Taraschi, Z. Y. Cheng, D. A. Antoniadis, C. S. Tan, S. Chattopadhyay, H. Zhao, P. S. Lee, L. Miao, S. J. Chua, K. L. Pey, and W. K. Choi, “The Relaxed SiGe Materials Platform: Strained Si MOS,” Proceeding of the Singapore-MIT Alliance Annual Symposium, National University of Singapore, January 16-17, 2001.

(5)    (Invited) R. Reif, C. S. Tan, A. Fan, K. N. Chen, S. Das, and N. Checka, “

(6)   3-D Interconnects Using Cu Wafer Bonding : Technology and Applications,” Adcanced Metallization Conference (AMC), October 1-3, 2002, San Diego, CA. In Melnick et al, Advanced Metallization Conference 2002, Materials Research Society, pp 37-45, Spring 2003.

(6)   K. N. Chen, A. Fan, C. S. Tan, and R. Reif, “Temperature and Duration Effect on Microstructure Evolution During Copper Wafer Bonding,” TMS Annual Meeting, San Diego, CA, March 2-6,  2003.

(7)   K. N. Chen, A. Fan, C. S. Tan, and R. Reif, "Relation of contact resistance and parameters of bonded Cu interconnects in three-dimensional integration technology," Proceedings of 2003 Electrochemical Society Meeting, vol 2003-10, pp1-5, Orlando, FL, October 2003.

(8)   K.N. Chen, A. Fan, C. S. Tan, and R. Reif, "Abnormal Contact Resistance Reduction in Bonded Cu Interconnects Using Pre-Bonding HCl Cleaning,” MRS Fall Meeting, Boston, MA, December 2003.

(9)   (Invited) R. Reif, S. Das, A. Fan, K. N. Chen, C. S. Tan, and N. Checka, “Technology, Performance, and Computer-Aided Design of Three-Dimensional Integrated Circuits,” International Symposium on Physical Design (ISPD 2004), Phoenix, Arizona, April 18-21, 2004.

(10)                        (Invited) R. Reif, C. S. Tan, A. Fan, K. N. Chen, S. Das, and N. Checka, "Technology and Applications of Three-Dimensional Integration,” 206^th Electrochemical Society Fall Meeting, Honolulu, Hawaii, October 3-8, 2004. In Dielectrics for Nanosystems: Materials, Science, Processing, Reliability, and Manufacturing, R. Singh, H. Iwai, R. R. Tummala, and S. C. Sun, Editors, PV 2004-04, The Electrochemical Society Proceedings Series, Pennington, NJ, 2004.

(11)C. S. Tan, A. Fan, K. N. Chen, and R. Reif, “Multilayered Three-Dimensional Integration Enabled by Wafer Bonding,” SRC/ISMT 7^th Annual Topical Research Conference on Reliability, University of Texas, Austin, TX, October 25-27, pp. 27, 2004.

(12)                        K. N. Chen, C. S. Tan, A. Fan, and R. Reif, “Effects of surface roughness and oxide formation of Cu film on the quality of Cu wafer bonding”, TMS Annual Meeting, San Francisco, CA, February 13-17, 2005.

(13)                        K. N. Chen, A. Fan, C. S. Tan, and R. Reif, “Bonding parameters of Cu wafer bonding for 3D Integration”, TMS Annual Meeting, San Francisco, CA, February 13-17, 2005.

(14)                        C. S. Tan and R. Reif, “Three-Dimensional (3-D) Silicon Multi-layer Stacking,” RTI 2^nd 3D Architectures for Semiconductor Integration and Packaging Conference, Tempe, AZ, June 13-15, 2005.

(15)C.  S. Tan, K. N. Chen, A. Fan, and R. Reif, “A Back-to-Face Silicon Layer Stacking for Three-Dimensional Integration,” IEEE International SOI Conference, Honolulu, HI, pp 87-89, October 3-6, 2005.

(16)                        (Invited) C. S. Tan, K. N. Chen, A. Fan, R. Reif, and A. Chandrakasan, “Silicon Layer Stacking Enabled by Wafer Bonding,” MRS Fall Meeting, Boston, MA, Nov 27 – Dec 1, 2006.

(17)                        (Invited) C. S. Tan, A. Chandrakasan, and R. Reif, “Progress in Copper-based Wafer Bonding,” 24^th International VLSI/ULSI Multilevel Interconnection Conference, Fremont, CA, September 24 – 27, 2007.

(18)                        (Invited) C. S. Tan, “Copper Bonded 3-D ICs and Its Thermal Characteristics”, Sematech Workshop on Thermal and Design Issues in 3D ICs,  Albany, NY, October 11-12, 2007.

(19) C. S. Tan, "Thermal Stress Analysis of Cu-Bonded Silicon Double-Layer Stack," 3D System Integration Conference, Tokyo, Japan, May 12-13, 2008.

(20) (Invited) C. S. Tan, "Recent Progress in Copper-based Wafer Bonding for 3-D ICs Applications," Joint International Microsystems, Packaging, Assembly Circuits Technology Conference (IMPACT) and International Conference on Electronics Materials and Packaging (EMAP), Taipei, Taiwan, October 22-24, 2008.

(21)  (Invited) C. S. Tan, “On Wafer 3D/Vertical Integration of Integrated Circuits,” IEEE International Workshop on Next Generation Electronics (IWNE), Tainan, Taiwan, November 20-21, 2008.

 

 

Invited Talks / Presentations (Presenter is underlined)

 

(1)     R. Reif, C. S. Tan, A. Fan, K. N. Chen, S. Das, and N. Checka, "3-D Integration using Cu-Cu Wafer Bonding," DARPA 3-D Microelectronics Integration Workshop, San Diego, CA, July 10, 2002.

(2)    R. Reif, C. S. Tan, A. Fan, and K. N. Chen, “Three-dimensional Integration Enabled by Wafer Bonding and Layer Transfer,” Presented at Applied Materials Inc, Santa Clara, CA, January 16, 2004.

(3)    R. Reif, C.S. Tan, A. Fan, K. N. Chen, S. Das, and N. Checka, "Technology and Applications of Three-Dimensional Integration,” Pre-conference Symposium, RTI/ISMT 3D Architectures for Semiconductor Integration and Packaging Conference, April 13-15, 2004, Burlingame, CA.

(4)    R. Reif and C. S. Tan, “Three-Dimensional Technology for Integrated Circuits,” 2004 MIT Electronics and Semiconductor Conference, Industrial Liaison Program, November 16-17, 2004, MIT, Cambridge, MA.

(5)     C. S. Tan and R. Reif, “Sky is the Limit: Multi-layer Three-Dimensional Integration Achieved by Wafer Bonding” Nanyang Technological University, Jan 27, 2005, Singapore.

(6)    C. S. Tan, “Wafer level 3-D ICs,” 2^nd Pall-NTU Technology Workshop on Si-based Nanodevices, May 21, 2007,  Nanyang Technological University, Singapore.

(7)    C. S. Tan, “Progress in Copper-Based Wafer Bonding and Its Applications in 3-D ICs,” Microelectronics Research Center, Georgia Institute of Technology, Atlanta, GA, USA, December 13, 2007.

(8)    (Short Course) C. S. Tan, “Wafer Level 3-D Integration,” Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, February 25, 2008.

 

 

Patents

 

(1)    Rafael Reif, Kuan-Neng Chen, Chuan Seng Tan, and Andy Fan, “Method of Forming A Multi-Layer Semiconductor Structure Incorporating A Processing Handle Member,” US 7,307,003 (December 11, 2007).

(2)    Rafael Reif, Kuan-Neng Chen, Chuan Seng Tan, and Andy Fan, “Method of Forming a Multi-Layer Semiconductor Structure Incorporating a Processing Handle Member,” US Patent Application 2008/0064183 (March 13, 2008).

 

 

 

Thesis

 

(1)    “ECG Signals Classification Using Artificial Neural Network,” B.Eng Thesis, University of Malaya, Malaysia, 1999.

(2)   “Rapid Thermal Oxidation of strained-Si/relaxed-SiGe Heterostructure,” M.Eng Thesis, Singapore-MIT Alliance, National University of Singapore, Singapore, 2001.

(3)   “Multi-layer Three-Dimensional Silicon Electronics Based on Wafer Bonding,” Ph.D. Thesis, Massachusetts Institute of Technology, USA, 2006.