PUBLICATIONS

PLLs ADCs RF Circuits & System Biomedical & Emerging Tech. Digital

PLLs and building blocks for RF tranceivers and clock generation

JOURNAL

J. Lee, S. Park and S.H. Cho, "A 470-uW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider with an In-Phase Dual-Input Injection Scheme" IEEE Transactions on Very Large Scale Integrated Systems, Vol. 19, No. 1, pp. 61-70, Jan. 2011.
P.W. Park, D.Park and S.H. Cho, "A Low-Noise and Low-Power Frequency Synthesizer using Offset Phase-Locked Loop in 0.13-mm CMOS" IEEE Microwave and Wireless Components Letters,Vol. 20, No. 1, Jan. 2010.
D. Park and S.H. Cho, "Design Techniques for a Low-voltage VCO with Wide Tuning Range and Low Sensitivity to Environmental Variations" IEEE Transactions on Microwave Theory and Techniques, April, 2009.
D. Park and S.H. Cho, "A 1.8 V 900-uW 4.5 GHz VCO and Prescaler in 0.18um CMOS Using Charge-Recycling Technique" IEEE Microwave and Wireless Components Letters, February, 2009.
J. Lee, S. Kim, S. Jeon, W. Lee, and S.H. Cho, "A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13 um CMOS" IEICE Electronics, Vol. E92-C, No. 4, pp.589-591, April, 2009.
S.H. Cho,"A Self Noise Canceling Technique for Voltage-Controlled Oscillators", IET Electronics Letters, Vol. 44, No. 25, 2008.
J.H. Han and S.H. Cho,"Digitally Controlled Oscillator with High Frequency Resolution using Novel Varactor Bank", IET Electronics Letters, Vol. 44, No. 25, 2008.
Y. Ku and S.H. Cho,"An Optimum Current Mirror Ratio for Low Phase Noise LC-VCO ", IEEE Microwave and Wireless Components Letters, Vol. 18, No. 12, 2008.
Y. Ku, I. Nam, S. ha, K. Lee, S.H. Cho,"Close-in Phase-Noise Enhanced Voltage-Controlled Oscillator Employing Parasitic V-NPN Transistor in CMOS Process", IEEE Transactions on Microwave Theory and Techniques ,Vol.54, No.4, pp.1363-1369, April 2006.
G. Manganaro, S.-U. Kwak, S.H. Cho, A. Pulincherry, "A Behavioral Modeling Approach to the Design of a Low Jitter Clock Source", IEEE Transactions on Circuits and Systems -II: Analog and Digital Signal Processing, Vol. 50, No.11, Nov. 2003, pp.804-814.

CONFERENCE

P.W. Park, D.Park and S.H. Cho, "A Fractional-N Frequency Synthesizer using High-OSR Delta-Sigma Modulator and Nested-PLL" IEEE Custom Integrated Circuits Conference, 2011.
W.Lee and S.H. Cho ,"A 2.4-GHz Reference Doubled Fractional-N PLL with Dual Phase Detector in 0.13-um CMOS" IEEE Int'l Symp. on Circuits and Systems (ISCAS), 2010.
S.-P. Lee and S.H. Cho, "A background KDCO compensation technique for constant bandwidth in all-digital phase-locked loop; IEEE Int'l Symp. on Circuits and Systems (ISCAS), 2010.
W. Lee and S.H. Cho, "A 900 MHz 2.2 mW Spread Spectrum Clock Generator based on Direct Frequency Synthesis and Harmonic Injection Locking", International SoC Conference(ISOCC), 2009.
S.-J. Kim and S.H. Cho "A Variation Tolerant Reconfigurable Time Difference Amplier", International SoC Conference(ISOCC), 2009.
D. Park , W. Lee, S. Jeon, S. Cho,"A 2.5-GHz 860μW charge-recycling fractional-N frequency synthesizer in 130nm CMOS", IEEE Symposium on VLSI Circuits, pp. 88 - 89, 2008.
J. Lee, K. Kim, J. Lee, T. Jang, S.H. Cho,"A 480-MHz to 1-GHz Sub-picosecond Clock Generator with a Fast and Accurate Automatic Frequency Calibration in 0.13-um CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 67 - 70, 2007.
J. Lee, S.H. Cho,"A 470-uW Multi-Modulus Injection-Locked Frequency Divider with Division Ratio of 2, 3, 4, 5, and 6 in 0.13-um CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 332 - 335, 2007.
D. Park, S.H. Cho,"An Adaptive Body-Biased VCO with Voltage-Boosted Switched Tuning in 0.5-V Supply", European Solid-State Circuits Conference (ESSCIRC),pp. 444 - 447, 2006.
D. Park, S.H. Cho,"A Power-Optimized CMOS LC VCO with Wide Tuning Range in 0.5-V Supply", IEEE International Conference on Circuits and Systems (ISCAS), pp. 3233 - 3236, 2006.

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Analog-to-Digital Converters

JOURNAL

T. K. Jang, J. Kim, Y.-G. Yoon and S.H. Cho, “A Highly-Digital VCO-based Analog-to-Digital Converter using Phase Interpolator and Digital Calibration,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), to appear.
K.S. Kim, J. Kim and S.H. Cho,"nth-order multi-bit SD ADC using SAR quantiser", IET Electronics Letters, Vol. 46, No. 19, 2010.
J. Kim, T.-K. Jang, Y.-G. Yoon and S.H. Cho, "Analysis and Design of Voltage-Controlled Oscillator-Based Analog-to-Digital Converter" IEEE Transactions on Circuits and Systems I, Vol. 57, No. 1, pp. 18-30, Jan 2010.
Y.-G. Yoon, J. Kim, T.K. Jang and S.H. Cho,"A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators", IEEE Transactions on Circuits and Systems I ,Vol. 55, No.11, pp. 3571-3581, December 2008. (Winner of the 2009 IEEE Transactions on Circuits and Systems Guillemon-Cauer Best Paper Award)

CONFERENCE

Y.-H. Kim and S.H. Cho ,"A 10-bit 300MSample/s Pipelined ADC using Time-Interleaved SAR ADC for Front-End Stages" IEEE Int'l Symp. on Circuits and Systems (ISCAS), 2010.
Y.-G. Yoon and S.H. Cho,"A 1.5-GHz 63dB SNR 20mW Direct RF Sampling Bandpass VCO-based ADC in 65nm CMOS", IEEE Symposium on VLSI Circuits, pp.270-271, June 2009.
Y.-H. Kim and S.H. Cho, "A Time-based Successive Approximation Register Analog-to-Digital Converter using a Pulse Width Modulation Technique with a Single Capacitor", International SoC Conference(ISOCC), 2009.
Y.-G. Yoon and S.H. Cho, "A Linearization Technique for Voltage-Controlled Oscillator-based ADC", International SoC Conference(ISOCC), 2009.
J. Kim, S.H. Cho, "A Time-Based Analog-to-Digital Converter Using a Multi-Phase Voltage-Controlled Oscillator", IEEE International Conference on Circuits and Systems (ISCAS), pp. 3934 - 3937, 2006.
S.H. Cho, S.M. Ock, S.H. Lee, J. Lee, "A Low Power Pipelined Analog-to-Digital Converter using Series Sampling Capacitors", IEEE International Conference on Circuits and Systems (ISCAS), pp. 6178 - 6181, 2005.
K. Gulati, C. Munoz, S.H. Cho, G. Manganaro, M. Lugin, M. Peng, A. Pulincherry, J. Li, A. Bugeja, A. Chandrakasan and D. Shoemaker, "A Highly Integrated Analog Base-band Transceiver Featuring a 12-bit 180MSPS Pipelined A/D Converter for Multi-Channel Wireless LAN", IEEE Symposium on VLSI Circuits, 2004.

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RF Communication Circuits and Systems

JOURNAL

J. Lee, S.H. Cho,"A Quadrature Modulation Transmitter Using Two Frequency Synthesizers", IEEE Transactions on Circuits and Systems II ,Vol.54, No.10, pp.907-911, October 2007.
J. Lee, I. Nam, S.H. Cho, K. Lee,"A Highly Linear and Nos Noise 2.4-GHz RF Front-End Circuits Using Transformer and Vertical NPN BJT", IEE Electronics Letters ,Vol.43, No.2, pp.103-105, January 2007.
S.H. Cho, A. Chandrakasan,"A 6.5GHz CMOS FSK modulator for wireless sensor applications", IEEE Journal of Solid-State Circuits, Vol.39, No.5, pp.731-739, May 2004.

CONFERENCE

J.Kim, S.H. Cho, "Digital-Intensive Analog Circuits for Highly-Digitized RF Receivers," IEEE Intenationa Midwest Symposium on Circuits and Systems (MWSCAS), 2011.
J. Kim, W. Yu and S.H. Cho,"A Digital-Intensive Receiver Front-End Using VCO-Based ADC with an Embedded 2nd-Order Anti-Aliasing Sinc Filter in 90nm CMOS,",IEEE International Solid-State Circuits Conference (ISSCC), 2011.
J. Lee, J. Kim and S.H. Cho, "A 1.8 to 2.4-GHz 20mW digital-intensive RF sampling receiver with a noise-canceling bandpass low-noise amplifier in 90nm CMOS," IEEE RFIC Symposium, 2010.
J. Lee, S. Cho,"A Low Power Transmitter for Phase Shift Keying Modulation Schemes", Proceedings of IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), 2006.
S.H. Cho, A. Chandrakasan, "A 6.5GHz CMOS FSK modulator for wireless sensor applications", IEEE Symposium on VLSI Circuits, pp.182-185, 2002.

Biomedical Circuits, Wireless Sensors and Emerging Applications

JOURNAL

S.J. Kim, M.C. Cho, S.H. Cho,"An Ultra Low Power and Variation Tolerent GEN2 RFID Tag Front-End with Novel Clock-Free Decoder ", IEICE TRANSACTIONS on Electronics, Vol.E93-C,No.6,pp785-795,2010.
B.H. Calhoun, D. Daly, N. Verma, D. Finchelstein, D.D. Wentzloff, A. Wang, S.H. Cho, A. P. Chandrakasan"Design Considerations for Ultra-low Energy Wireless Microsensor Nodes", IEEE Transactions on Computers,Vol.54, No.6, pp.727-740, June 2005.
E. Shih, S.H. Cho, F.S. Lee, B Calhoun, and A. Chandrakasan, "Design considerations for energy-efficient radios in wireless microsensor networks", Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, Vol.39, No.5, May 2004, pp.77-94.
R. Min, M. Bhardwaj, S.H. Cho, N. Ickes, E. Shih, A. Sinha, A. Wang, A. Chandrakasan, "Energy-centric enabling technologies for wireless sensor networks", IEEE Wireless Communications, Vol. 9, No. 4, pp. 28-39, Aug., 2002.

CONFERENCE

Junghyup Lee and SeongHwan Cho, "A 210 nW 29.3 ppm/C 0.7 V Voltage Reference with a Temperature Range of -50 to 130 C in 0.13 um CMOS" IEEE Symposium on VLSI Circuits, June 2011.
W. Lee, M.C. Cho, S.H. Cho, "CMRR enhancement technique for IA using three IAs for bio-medical sensor applications" IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2010.
K. Choo, W. Lee, S.H. Cho, "A PVT Tolerant BPF using Turn-off MOSFET for Bio Applications in 0.13um CMOS" International SoC Conference(ISOCC), 2010.
S. Sehyung Jeon, Yoonkey Nam and SeongHwan Cho, "A Neural Recording and Stimulation Technique using Passivated Electrodes and Micro-Inductors" IEEE Asian Solid-State Circuits Conference(ASSCC), 2009.
J. Lee and S.H. Cho,"A 10MHz, 80uW, 67 ppm/degree CMOS Reference Clock Oscillator with a Temperature Compensated Feedback Loop in 0.18um CMOS", IEEE Symposium on VLSI Circuits, June 2009.
S.H. Park, C.W. Min, S.H. Cho,"A 95nW Ring Oscillator-based Temperature Sensor for RFID Tags in 0.13um CMOS", IEEE International Symposium on Circuit and System (ISCAS), 2009
M.C. Cho, J.Y. Kim, S.H. Cho ,"A Bio-Impedance Measurement System for Portable Monitoring of Heart Rate and Pulse Wave Velocity Using Small Body Area,", IEEE International Symposium on Circuit and System (ISCAS), 2009
S. Bang, C. Lee, J. Park, M.-C. Cho, Y.-G. Yoon, S.H. Cho, "A Pulse Trasit Time Measurement Method Based on Electrocardiography and Bioimpedance" IEEE Biomedical Circuits and Systems Conference (BioCAS), 2009.
M.-C. Cho, Y.-G. Yoon and S.H. Cho "Design of Highly Programmable Bio-Impedance Measurement IC in 0.18um CMOS", International SoC Conference(ISOCC), 2009.
S.-S. Woo and S.H. Cho "A Ring Oscillator-based Temperature Sensor for U-Healthcare in 0.13um CMOS", International SoC Conference(ISOCC), 2009.
S.J. Kim, M.C. Cho, J. Park, K. Song, Y. Kim, S.H. Cho,"An ultra low power UHF RFID tag front-end for EPCglobal Gen2 with novel clock-free decoder", IEEE International Symposium on Circuit and System (ISCAS) , pp. 660 - 663, 2008.
S.H. Cho, K.E. Kim, "Variable Bandwidth Allocation Scheme for Energy Efficient Wireless Sensor Network", IEEE International Conference on Communications (ICC), pp.3314 - 3318, 2005.
A. Chandrakasan, R. Min, M. Bhardwaj, S.H. Cho, and A. Wang, "Power Aware Wireless Microsensor Systems", (Keynote paper, Invited) Proceedings of ESSCIRC, pp.47-54, 2002.
A. Wang, S.H. Cho, C. Sodini, A. Chandrakasan, "Energy Efficient Modulation and MAC for Asymmetric RF Microsensor systems", Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design, pp.106-111, 2001.
E. Shih, S.H. Cho, N. Ickes, R. Min, A. Sinha, A. Wang, and A. Chandrakasan, "Physical Layer Driven Algorithm and Protocol Design for Energy-Efficient Wireless Sensor Networks", Proceedings of ACM/IEEE International Conference on Mobile Computing and Networking (MOBICOM), pp.272-287, 2001.
S.H. Cho, A. Chandrakasan, "Energy Efficient Protocols for Low Duty Cycle Wireless Microsensor Networks", Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) , pp.2041-2044, 2001.
E. Shih, S.H. Cho, B. Calhoun, A. Chandrakasan, "Energy Efficient Link Layer for Wireless Microsensor Networks", Proceedings of IEEE Workshop on VLSI, pp.16-21, 2001.
R. Min, M. Bhardwaj, S.H. Cho, A. Sinha, E. Shih, A. Wang and A. Chandrakasan, "An Architecture for a Power-Aware Distributed Microsensor Node", IEEE Workshop on Signal Processing Systems (SiPS '00), pp.581-590, 2000.
A. Chandrakasan, R. Amirtharajah, S.H. Cho, J. Goodman, G. Konduri, J. Kulik, W. Rabiner, A. Wang, "Design Considerations for Distributed Microsensor Systems", Proceedings of the IEEE Custom Integrated Circuits Conference, pp.279-286, 1999.

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Digital Circuits & Systems

J. Lee, W. Lee and S.H. Cho, "A 2.5-Gb/s On-Chip Interconnect Transceiver with Crosstalk and ISI Equalizer in 130nm CMOS", IEEE Transactions on Circuits and Systems I, to appear.
H. Chung, E Hong, K Kim, S.H. Cho,"Optimum Supply Voltage and Sleep Transistor Sizing for Energy Minimization in Latency-Constrained MTCMOS Circuits", International SoC Design Conference(ISOCC), pp. 365 - 368, 2006.
A. Chandrakasan, Rajeevan Amirtharajah, S.H. Cho, James Goodman, Gangadhar Konduri, Joanna Kulik, Wendi Rabiner, Alice Wang, "Design Considerations for Distributed Microsensor Systems Part I & II, "What's New in Electronics"
Part I: vol.20, no.8, Jan. 2001, pp.25-28.
Part II: vol.20, no.9, Feb. 2001, pp.24-25.
R. Min, M. Bhardwaj, S.H. Cho, E. Shih, A. Sinha, A. Wang and A. Chandrakasan, "Low-Power Wireless Sensor Networks", IEEE Fourteenth International Conference on VLSI Design, pp.205-210, 2001.
S.H. Cho, T. Xanthopoulos and A. Chandrakasan, "A Low Power Variable Length Decoder for MPEG-2 Based on Nonuniform Fine-Grain Table Partitioning", IEEE Transactions on VLSI Systems, vol.7, no.2, June 1999, pp.249-257.
S.H. Cho, T. Xanthopoulos and A. Chandrakasan, "An Ultra Low Power Variable Length Decoder Exploiting Codeword Distribution", Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 177-180, 1998.
S.H. Cho, T. Xanthopoulos and A. Chandrakasan, "Design of Low Power Variable Length Decoder Using Fine Grain Non-Uniform Table Partitioning", IEEE International Symposium on Circuits and Systems, pp. 2156-2159, 1997.

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