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• Ph.D. in Computer Engineering, Iowa State University, Ames, IA, USA, 2008.
  
• Adviser: Dr. Zhao Zhang
• Thesis: Thermal Modeling and Management of DRAM Memory Systems.
• BS in Computer Science, Huazhong University of Science and Technology, Wuhan, China, 1998.
  

• Enigma: Architectural and Operating System Support for Reducing the Impact of Address Translation. (ICS'10)
  
• Enabling Software Management for Multicore Cache with Lightweight Hardware Support. (SC'09)
  
• Soft-OLP: Improving Hardware Cache Performance Through Software-Controlled Object-Level Cache Partitioning. (PACT'09)
  
• Decoupled DIMM: Building High-Bandwidth Memory System from Low-Speed DRAM Devices. (ISCA'09)
• Mini-Rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency. (MICRO'08)
• Software Thermal Management of DRAM Memory for Multicore Systems. (SIGMETRICS'08)
• Gaining Insights into Multicore Cache Partitioning: Bridging the Gap between Simulation and Real Systems. (HPCA'08)
• Thermal Modeling and Management of DRAM Memory Systems. (ISCA'07)

• Senior Design Engineer, 09/2010 - Now, AMD, Austin, TX
  
• Senior Software engineer, 12/2009 - 08/2010, Intel, Hillsboro, OR
  
• Postdoctoral researcher, 08/2008 - 11/2009, IBM Research, Austin, TX
  
• Research assistant, 9/2003 - 08/2008. Iowa State University, Ames, IA
• Software engineer and master student, 09/2001 - 07/2003, North China Institute of Computing Technology, Beijing, China.
• Software engineer, 08/1998 - 08/2001, Huawei Technologies, Shenzhen, Guangdong, China

• Program Committee Member: NAS 2009,
  
• Reviewer for ICPP 2009, Sigmetrics 2008, 
  
• Reviewer for ACM Transactions in Embedded Computing Systems (TECS)
• Reviewer for IEEE Micro magazine, 
  
• Reviewer for Journal of Parallel and Distributed Computing - Elsevier,
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• Member of IEEE (since 2006)