Pittsburgh 412/802 0381
OBJECTIVE: To develop LAMP (software bundle) applications using multi-core CPUs. Multi-core is what makes the iPhone possible.
A multi-core CPU combines two or more independent cores into a single package comprised of a single piece of silicon integrated circuit , called die, or more dies packaged together. A dual-core device contains two independent microprocessors and a quad-core device contains four microprocessors. A multi-core microprocessor implements multiprocessing in a single physical package. Cores in a multicore device may share a single coherent cache at the highest on-device cache level (e.g. L2 for the Intel Core 2) or may have separate caches (e.g. current AMD dual-core processors). The processors also share the same interconnect to the rest of the system. Each "core" independently implements optimizations such as superscalar execution, pipelining, and multithreading. A system with N cores is effective when it is presented with N or more threads concurrently. The most commercially significant (or at least the most 'obvious') multi-core processors are those used in computers (primarily from Intel & AMD.) In this context, "multi" typically means a relatively small number of cores.Moore's Law doesn't really apply to mobile devices in the same way as to desktop and server applications. Moore's Law is actually a law about transistor density — that is, it says that you can pack more circuitry into a given chip size, over time. For desktop and server applications, this means you can pack more "speed" into a chip of roughly the same size, resulting in the well-known performance increases. For embedded applications like cell phones, however, Moore's Law is usually exploited to make chips smaller. That is, the tendency is to use the increased density to make the same chip smaller and consume less power, to make phones smaller and make batteries last longer. As a result, embedded devices like phones are increasing in actual, raw speed much more slowly than desktop systems. For embedded devices, Moore's Law means more features and better battery life; increased speed is only an afterthought. However, the technology is widely used and commercially significant in GPUs (Graphics Processing Units) like my experience at ATI/AMD. The raw compute performance of today’s graphics processor is truly amazing. With peak performance of over 1 teraFLOPS, the compute power of the graphics processor (GPU) dwarfs that of today’s commodity CPU at a price of only a few hundred dollars. As the programmability and performance of modern graphics hardware continues to increase, many researchers are looking to graphics hardware to solve computationally intensive problems previously performed on general purpose CPUs. The challenge, however, is how to re-target these processors from game rendering to general computation, such as numerical modeling, scientific computing, or signal processing.EDUCATION: Master’s of Science, Telecommunications, April 1998 University of Pittsburgh, Pittsburgh, PA
EXPERIENCE:Professional Education 12/2005 - 03/2008 Telecommunications Pittsburgh, PA
* Graduate Social Web Course CSS, DOM, Firebug, Ajax , Ruby on Rails
wget -r -l1 -H -t1 -nd -N -np -A.mp3 -erobots=off http://del.icio.us/tag/system:filetype:mp3+mashup
- Graduate Classes in Telephone Switching Systems 5ESS and PBX.
- Graduate Classes in Internet Telephony (VoIP.)
- Graduate Classes in Wireless Client/Server programming.
- Graduate Classes in Wireless Data Networks: EEE 802.11, BlueTooth.
- Graduate Classes in Java Programming and AJAX (Asynchronous JavaScript andXML.)
- Graduate Classes in Network Security and Cryptography.
- Doctoral seminar Nano electronics and Information Technology (Quantum Computing.)
- Graduate Classes in Quantum Mechanics.
- Graduate Super Computer (Cray) MPI, BLAS Programming. (SIMD)
- Graduate EE Classes in Multi core Computingg
- Computer Graphics and ray tracing at MIT
Work Experience
Atomated OpenGL/DirectX10 GPU graphics adapter driver Tester/Developer Automated Track/Signal Tester/Developer Manual Sonet Verification Tester
Automated Tester/Developer
Network Engineer
SVT - Systems Verification Tester.
Full Time Student at The University of Pittsburgh Full time Teacher Wall Street Prime Brokerage Network Engineer Merger and Acquisition Specialists
Developed Programmed Trading Algorithms (Black/Scholes) on Perkin-Elmer Dual-Core Main Frames Varityper Acquired the spin off of CMU research project:SPICE (Scientific Integral Computing Environment) Developed SPICE and Accent under the leadership of Rick Rashid.
Started my own Business. | 10/2006 – 09/2009 AMD (Advanced Micro Devices)/ATI Santa Clara, (Silicon Valley) CA Wrote and maintain object-oriented and procedural Perl and Python scripts to automate regression testing and development of the OpenGL driver for AMD /ATI “Radeon HD 2900 XTX Crossfire GPU “ on the 32/64 bit, quad-core CPU/GPU/VPU (Video Processing Unit) for the Ultimate MS Vista/XP/Linux 3D graphics pipeline for Blueray and HD DVD for High Definition Multimedia Interface (HDMI) players. Formatting and Configuring Apache, Perforce, Python, Perl, Cygwin:BASH, MySQL and PHP with SSH and VNC on an endless supply of new machines to build/unsubmit (clobber), test and display every phase of OpenGL driver development with Perforce. “Orca” development system is a client/server system: a farm of Apache Web servers and Wget calls full of “edge cases." 9/2006 - 10/2006 Union Switch and Signal, Pittsburgh, PAWrote object-oriented and procedural Perl code for railroad tracks (switch and signals) using MySQL with Linux/Perl 5. Regular expression pattern matching, hashing and database query caching in an object-oriented environment. All this designed in UML, Rational Rose (with Clear Case version control.) Moved code into proper package namespaces. Enabled strictures and warnings in multiple files. Reorganized code into CPAN-style distributions using Module::Build. Refactored& rewrote procedural code into object-oriented code. Extracted inline MySQL into an external dictionary. Organized tasks and tracked their dependencies. 9/2000 - 11/2005 Cisco Systems Petaluma, CA
Test the provisioning of circuits on using Cisco 6700 series. -An Integrated Digital Loop Carrier (High Speed Transmission Systems.) (Cisco certified in the 6700 - GR 303 series.) Working with Cerent OC-48 (2.5 Gb/s) ADM; Fireberd, Tberd and SONET Testers and Abacus Central Office simulator Also worked with the Hammer for VoATM. 3/2000 - 7/2000Lucent - Bell Labs North Andover, MA SVT Tester Wrote tester Perl scripts for OC-48 (2.5Gb/s) and OC-192 (10Gb/s) (High Speed Transmission Systems.) using Anritsu test set and HP VXI with GPIB to Ethernet converter: SONET 1/1999 - 2/2000 MCI Worldcomm Richardson, TX Network Engineer UUNET T1s & DS3s Tested on MCI's Network "Developer's Lab" in Richardson, TX. High Speed Transmission Systems. Working with Alcatel DACS OC-48 (2.5 Gb/s) ADM ; Fireberd, Tberd. Also worked with the Hammer for VoFrame Relay 8/1998 - 12/1998 AT&T Holmdel, NJ Tested Northern Telecom, Fujitsu and Lucent
OC-3 (155.52 Mb/s), OC-12 (622.08 Mb/s) TDM/ADM and Newbridge SONET/ATM for
private networks division. High Speed Transmission Systems. 2/1990 - 12/1994 Community College of Allegheny County Pittsburgh, PA UNIX/C++/Perl Instructor Unix Administrator and taught two classes twice a week. 1/1989 - 1/1990 Bear Sterns New York, NY Unix admin./ DBA Developed and maintained large Informix database of government securities with UNIX Bourne shell scripts on their Amdahl High Speed Transmission Systems. 12/1987 - 12/1988 Round Valley Computer Round Valley, NJ Network Installer Design, develop, install and repair PC networks for the large drug manufacturing companies on the New Jersey Coast with High Speed Transmission Systems. 8/1987 - 12/1987 Davis,Polk and Wardwell , 10 Wall Street New York, NY Software Engineer Developed Asbestos Litigation programs using Artificial Intelligence for Davis, Polk & Wardwell: The world largest Law Firm located across Wall St. from the NYSE using one of the first RISC UNIX computers and High Speed Transmission Systems. 1/1987 - 8/1987 J.J. Kenny, Broad Street, New York, N.Y. Software Engineer Took J.J. Kenny, the world's leading wholesale trader of Municipal bonds, from a $100 billions industry to a $200 billions industry in the wake of Reagan Era tax cuts. This company is now part of Rafferty Capital Markets, LLC. Worked with X.25 "Kenny Wire" :High Speed Transmission Systems. 6/1985 - 12/1986Varityper East Hanover, N.J. Software Engineer Developed Typesetting equipment (for the financial industry) connecting the fonts developed by the Parent Company: Adressagraph-Multigraph International (Similar to Adobe) with some of the then new user interface technology developed at Xerox PARC and High Speed Transmission Systems. 7/1983 - 10/1985 Carnegie-Mellon University Pittsburgh, PA Research Programmer Used the Accent API to create the distributed computing paradigm that would later become the Mach kernel and ultimately the MS Vista operating system. Computer processes communicating with each other over a TCP/IP network on High Speed Transmission Systems. 3/1982 - 7/1983 NORDECPittsburgh, PA Chief Consultant Computerized small manufacturing firms taking advantage of Reagan era accelerated depreciation tax
1/1981 - 3/1982 A.O. Management Pittsburgh, PA Programmer Developed trading progrms for highly leveraged commodity future contract investments. High speed transmission systems. |
