Contact Information

2600 SW Williston Road Apt 624

Gainesville, Florida  32608  USA

E-mail:  jpoe@ufl.edu

Work Status: U.S. Citizen

Objective

To obtain a full-time position which utilizes my knowledge and experience in computer systems, computer architecture and software development.

Education

University of Florida, Gainesville, Florida USA

      Ph.D., Electrical and Computer Engineering (expected graduation date: Dec 2009)

·      Dissertation Topic: Developing Representative Workloads for Future Hardware Transactional Memory Research using a Cycle-Accurate, Multi-Dimensional Hardware Transactional Memory Model

·      Advisor: Professor Tao Li

·      GPA: 4.00/4.00

      M.S., Electrical and Computer Engineering, May 2006

·      GPA: 4.00/4.00

Florida International University, Miami, Florida USA

      B.S., Computer Engineering, May 2004

·      Summa cum Laude

·      Chosen Spring 2004 Outstanding Graduate in Computer Engineering

·      GPA: 3.97/4.00

Research Projects

TransPlant is a framework for developing executable binaries designed to satisfy the statistical requirements of an input description file. This allows architects to quickly generate workloads that can be used to evaluate the performance of hardware modifications either within, or outside, the bounds of the limited set of available benchmarks. I proposed and was the lead developer on the TransPlant project. In addition to overall design, I was responsible for implementing the input statistics, workload layout and transaction/sequential cell placement.

SuperTrans, built on top of the SuperESCalar (SESC) chip multiprocessor simulator, is the first detailed, cycle accurate and multiple issue model of hardware transactional memory. It is capable of simulating all of the common dimensions of transactional memory (Eager/Eager, Eager/Lazy, Lazy/Lazy). I was responsible for its entire development, which included implementing proper memory emulation to ensure functional correctness, modifying the detailed pipeline for cycle accuracy, and designing coherence protocols for coordination.

TransMetric is a set of metrics and guidelines for use in architecturally independent characterization of transactional memory workloads. I was responsible for developing and validating the metrics, and with a co-author, used principle component analysis to perform a similarity study on the most common workload sets used in transactional memory research. We also developed methods for reducing simulation time through variable subsetting based upon the proposed metrics. 

BASS, a Benchmarking suite for evaluating Architectural Security Systems, is a collection of vulnerable programs and scripts for automatically generating exploits across different machines and multiple architectures. BASS exploits have been designed for diversity across multiple dimensions including vulnerability class, attack style, end result, memory location, code injection, and payload location. I was responsible for the entire development of BASS, including creation of the vulnerable programs, identification of the attack vectors, and development of tools to automatically synthesize the attacks across Alpha, x86, and M5 platforms. It has now been downloaded by more than 110 researchers in sectors including academia, industry and government.

The objective of this project was to explore methods that can effectively characterize microarchitectural vulnerability phase behavior for reliable processor architecture design. We observed that a single performance metric can not capture vulnerability phase behavior and evaluated the efficiency of program vulnerability phase classification methods using program-code structure and run-time events.

SimplePoint-MPI is a modified version of sim-outorder from the SimpleScalar simulation suite that has been modified to accept SimPoint generated simulation points and simulate them in parallel on a cluster of machines using MPI. SimplePoint-MPI statically allocates the points (generated using the SimPoint 2.0 algorithm) to the processors using an algorithm that determines that maximum parallelization based upon the fast forward distance required for each point. I was responsible for the development of the maximum parallelization algorithm as well as interfacing the SimpleScalar tool with SimPoint.

Publications

1.        James Poe, Clay Hughes and Tao Li, Understanding the Behavior of Hardware Transactional Memory Workloads: Observations, Implications and Design Recommendations,  submitted

2.        James Poe, Clay Hughes and Tao Li, On the (Dis)similarity of Transactional Memory Workloads, International Symposium on Workload Characterization (IISWC), October 2009

3.        James Poe, Clay Hughes and Tao Li, TransPlant: A Parameterized Methodology For Generating Transactional Memory Workloads, International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), September 2009

4.        Chang-Burm Cho, James Poe, Tao Li, and Jingling Yuan, Accurate, Scalable and Informative Design Space Exploration for Large and Sophisticated Multi-core Oriented Architectures, International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), September 2009

5.        James Poe, Clay Hughes and Tao Li, TransMetric: Architecture Independent Workload Characterization for Transactional Memory Benchmarks, International Conference on Supercomputing (ICS), June 2009

6.        James Poe, Chang-Burm Cho and Tao Li, Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-core Co-design, International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), October 2008

7.        James Poe and Tao Li, BASS: A Benchmarking Suite for evaluating Architectural Security Systems, Computer Architecture News (CAN), Volume 34, Issue 4, pages 26-33, December 2006

8.        Xin Fu, James Poe, Tao Li and Jose Fortes, Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior, International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), September 2006, (Nominated for best paper award)

9.        James Poe, Fernando Hernandez, and Tao Li, Reducing Simulation Time by Parallelizing SimpleScalar in MPI Through The Use of SimPoint Generated Intervals, Technical Report, IDEAL Research, ECE Dept., University of Florida, March 2005

Honors and Awards

·          National Science Foundation Graduate Research Fellowship  (NSF GRFP)

·          Travel Grant for 2009 International Conference on Supercomputing (ICS)

·          Travel Grant for 34th Annual International Symposium on Computer Architecture (ISCA-34)

·          Travel Grant for 33rd Annual International Symposium on Computer Architecture (ISCA-33)

·          Fellowship position in ECE Department of the University of Florida

·          Spring 2004 Outstanding Graduate in Computer Engineering at Florida International University

·          Engineering Leadership Award at Florida International University

·          Engineering Dean's Merit Scholarship Award

·          National Society of Collegiate Scholar's National Merit Award

·          Florida International University's Faculty Scholars Award and Scholarship

·          Florida Academic Scholars Award and Scholarship

Technical Skills

Programming: C, C++, Java, PHP, Lisp, UNIX shell scripting, SQL, Visual Basic, HTML

Simulators: Simics, SimpleScalar, SESC, M5, Cadence

Operating Systems: Linux, Unix, Windows

Relevant Coursework: Computer Architecture, Billion Transistor Architecture, Parallel Computing, Network Security, VLSI Design, Machine Intelligence, Financial Accounting, Global Management, Technology Management

Teaching Experience

University of Florida, Gainesville, Florida USA

Florida International University, Miami, Florida USA

Miami Palmetto Senior High School, Miami, Florida USA

Professional Talks

1.        ICS'09, TransMetric: Architecture Independent Workload Characterization for Transactional Memory Benchmarks, Nyack, New York, June 9, 2009

2.        SRC REVIEW’09, Developing Future Workloads for Future Hardware Transactional Memory Research, Stanford University, California, March 03, 2009

3.        SBAC-PAD'08, Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-core Co-design, Campo Grande, Brazil, October 30, 2008

4.        SBAC-PAD'08, ORBIT: Effective Issue Queue Soft-error Vulnerability Mitigation on Simultaneous Multithreaded Architectures using Operand Readiness-based Instruction Dispatch, Campo Grande, Brazil, October 30, 2008

5.        ASAP'08, Managing Multi-Core Soft-Error Reliability Through Utility-driven Cross Domain Optimization, Lueven, Belgium, July 3, 2008

6.        MASCOTS'06, Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior, Monterey, California, September 12, 2006

7.        IPCCC'06, OS-aware Tuning: Improving Instruction Cache Energy Efficiency on System Workloads, Phoenix, Arizona, April 11, 2006

Employment History

Quantum Consulting, Berkeley, California USA

Research Community Service

Workshop on the Interaction Between Operating Systems and Computer Architecture

Assorted Conferences and Journals

Professional Memberships

·          Tau Beta Pi national engineering honor society (TBP)

Served as President of Florida Theta chapter 2003-2004.

As president I presided over two of the largest induction ceremonies in recent years, left the organization with a substantial budget surplus, and at the end of my term was awarded the Secretary's Commendation from the national organization (an award our chapter hadn’t won in many years) as well as an Engineering Leadership Award from Florida International University.

Served as Vice-President of Florida Theta chapter 2002-2003.

As Vice-President I was responsible for scheduling guest speakers and in this capacity was able to set up all five Engineer Futures seminars that allowed many of our members to receive certification in this area.

·          Institute of Electrical and Electronics Engineers (IEEE)

Served as Vice-chair of FIU's student branch 2002-2003.

As Vice-chair I was primarily associated with fund raising activities. In this capacity I was able to raise enough funds to sponsor both a hardware and software team to compete in the annual IEEE Southeastern conference competition held in Ocho Rios, Jamaica.

·          Association for Computing Machinery Special Interest Group Computer Architecture (ACM SIGARCH).

·          Eta Kappa Nu national electrical engineering honor society (HKN).

·          Upsilon Pi Epsilon international computing sciences honor society (UPE).

·          Phi Kappa Phi national honor society (PKP).

·          National Society of Collegiate Scholars (NSCS).

·          Golden Key International honor society.

·          Member of the Order of the Engineer.

References

Available upon request